Detail publikace

Shadow filters based on DDCC

Originální název

Shadow filters based on DDCC

Anglický název

Shadow filters based on DDCC

Jazyk

en

Originální abstrakt

This paper presents a new realization of voltage-mode shadow filters based on low-voltage low-power differential difference current conveyor (DDCC). Thanks to the attractive features of the DDCC, including its capability of performing arithmetic operations, the proposed filters offer the advantage of circuit simplicity, minimum number of active and passive elements, and no need for additional summing circuit, compared to the previous available shadow filter designs. The DDCC was designed and fabricated in Cadence platform using 0.35 um CMOS AMIS process with supply voltage and power consumption of 1 V and 37 uW, respectively. The presented simulation and experimental results using a real chip validate the functionality of the proposed filters.

Anglický abstrakt

This paper presents a new realization of voltage-mode shadow filters based on low-voltage low-power differential difference current conveyor (DDCC). Thanks to the attractive features of the DDCC, including its capability of performing arithmetic operations, the proposed filters offer the advantage of circuit simplicity, minimum number of active and passive elements, and no need for additional summing circuit, compared to the previous available shadow filter designs. The DDCC was designed and fabricated in Cadence platform using 0.35 um CMOS AMIS process with supply voltage and power consumption of 1 V and 37 uW, respectively. The presented simulation and experimental results using a real chip validate the functionality of the proposed filters.

BibTex


@article{BUT136260,
  author="Fabian {Khateb} and Winai {Jaikla} and Tomasz {Kulej} and Montree {Kumngern} and David {Kubánek}",
  title="Shadow filters based on DDCC",
  annote="This paper presents a new realization of voltage-mode shadow filters based on low-voltage low-power differential difference current conveyor (DDCC). Thanks to the attractive features of the DDCC, including its capability of performing arithmetic operations, the proposed filters offer the advantage of circuit simplicity, minimum number of active and passive elements, and no need for additional summing circuit, compared to the previous available shadow filter designs. The DDCC was designed and fabricated in Cadence platform using 0.35 um CMOS AMIS process with supply voltage and power consumption of 1 V and 37 uW, respectively. The presented simulation and experimental results using a real chip validate the functionality of the proposed filters.",
  address="INST ENGINEERING TECHNOLOGY-IET",
  chapter="136260",
  doi="10.1049/iet-cds.2016.0522",
  howpublished="print",
  institution="INST ENGINEERING TECHNOLOGY-IET",
  number="6, IF: 1.092",
  volume="2017 (11)",
  year="2017",
  month="june",
  pages="631--637",
  publisher="INST ENGINEERING TECHNOLOGY-IET",
  type="journal article"
}