Detail publikace

Software Fault Tolerance: the Evaluation by Functional Verification

Originální název

Software Fault Tolerance: the Evaluation by Functional Verification

Anglický název

Software Fault Tolerance: the Evaluation by Functional Verification

Jazyk

en

Originální abstrakt

The aim of this paper is to present a new approach in evaluating Software Fault Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance without any additional hardware as is common in frequently used Triple Modular Redundancy (TMR). As our research is focused on electromechanical systems which are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we decided to use the soft-core processor running on Field Programmable Gate Array (FPGA) as our experimental platform. The new approach uses Functional Verification for automation of the evaluation process. The functional verification environment is one of the important parts of the presented evaluation platform architecture. Programs generation for a processor, where SFT is applied, is also important. Experiments with the programs generator and fault injection are presented and goals for future work are identified on that basis.

Anglický abstrakt

The aim of this paper is to present a new approach in evaluating Software Fault Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance without any additional hardware as is common in frequently used Triple Modular Redundancy (TMR). As our research is focused on electromechanical systems which are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we decided to use the soft-core processor running on Field Programmable Gate Array (FPGA) as our experimental platform. The new approach uses Functional Verification for automation of the evaluation process. The functional verification environment is one of the important parts of the presented evaluation platform architecture. Programs generation for a processor, where SFT is applied, is also important. Experiments with the programs generator and fault injection are presented and goals for future work are identified on that basis.

BibTex


@inproceedings{BUT119910,
  author="Ondřej {Čekan} and Jakub {Podivínský} and Zdeněk {Kotásek}",
  title="Software Fault Tolerance: the Evaluation by Functional Verification",
  annote="The aim of this paper is to present a new approach in evaluating Software Fault
Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance
without any additional hardware as is common in frequently used Triple Modular
Redundancy (TMR). As our research is focused on electromechanical systems which
are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we
decided to use the soft-core processor running on Field Programmable Gate Array
(FPGA) as our experimental platform. The new approach uses Functional
Verification for automation of the evaluation process. The functional
verification environment is one of the important parts of the presented
evaluation platform architecture. Programs generation for a processor, where SFT
is applied, is also important. Experiments with the programs generator and fault
injection are presented and goals for future work are identified on that basis.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the 18th Euromicro Conference on Digital Systems Design",
  chapter="119910",
  doi="10.1109/DSD.2015.107",
  edition="NEUVEDEN",
  howpublished="electronic, physical medium",
  institution="IEEE Computer Society",
  year="2015",
  month="august",
  pages="284--287",
  publisher="IEEE Computer Society",
  type="conference paper"
}