Detail publikace

FPGA Prototyping and Accelerated Verification of ASIPs

Originální název

FPGA Prototyping and Accelerated Verification of ASIPs

Anglický název

FPGA Prototyping and Accelerated Verification of ASIPs

Jazyk

en

Originální abstrakt

In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.

Anglický abstrakt

In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.

BibTex


@inproceedings{BUT119854,
  author="Jakub {Podivínský} and Marcela {Zachariášová} and Ondřej {Čekan} and Zdeněk {Kotásek}",
  title="FPGA Prototyping and Accelerated Verification of ASIPs",
  annote="In current SoC verification, the trend is to create verification solutions that
are tailored to specific issues in SoC or to specific architectures. The reason
is that the complexity of these systems makes it difficult to use general
verification approaches such as formal or simulation-based verification. This
paper presents a solution that is targeted to one particular area -
Application-Specific Instruction-Set Processors (ASIP) and multi-processor
systems containing several ASIPs. We propose automated FPGA prototyping and
accelerated verification of these systems while the accelerated verification
environment corresponds to the principles of UVM (Universal Verification
Methodology) therefore can easily be integrated. Automated generation of
verification environments and acceleration of verification runnning on a real
hardware platform makes this solution very unique and beneficial, not only in
speed, but also in debugging specific hardware issues.",
  address="IEEE Computer Society",
  booktitle="IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  chapter="119854",
  doi="10.1109/DDECS.2015.33",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2015",
  month="april",
  pages="145--148",
  publisher="IEEE Computer Society",
  type="conference paper"
}