Detail publikace

Synthesis Methodology of Polymorphic Circuits Using Polymorphic NAND/NOR Gates

Originální název

Synthesis Methodology of Polymorphic Circuits Using Polymorphic NAND/NOR Gates

Anglický název

Synthesis Methodology of Polymorphic Circuits Using Polymorphic NAND/NOR Gates

Jazyk

en

Originální abstrakt

In this paper, a novel approach dealing with the issues of multifunctional (polymorphic) logic circuits synthesis is presented. Crucial notion behind the polymorphic concept resides in the fact that such kind of circuit is able to perform more than one logic function, while the underlying structure keeps its arrangement untouched. The outlined behaviour is established by means of utilizing special multifunctional components (gates) during circuit design phase, where the individual connections among them remains unchanged (no reconfiguration takes place). The exact function, which the circuit is purposely executing at a given moment, is determined by the actual operating environment (e.g. supply voltage, temperature or a special signal). The proposed synthesis method is based on a formal Boolean representation of corresponding functions. Its main advantage can be recognized in strictly rigid and algorithmic notation with the employment of minimization techniques, which is in a direct contrast to competitive solutions, predominantly based on heuristic approaches.

Anglický abstrakt

In this paper, a novel approach dealing with the issues of multifunctional (polymorphic) logic circuits synthesis is presented. Crucial notion behind the polymorphic concept resides in the fact that such kind of circuit is able to perform more than one logic function, while the underlying structure keeps its arrangement untouched. The outlined behaviour is established by means of utilizing special multifunctional components (gates) during circuit design phase, where the individual connections among them remains unchanged (no reconfiguration takes place). The exact function, which the circuit is purposely executing at a given moment, is determined by the actual operating environment (e.g. supply voltage, temperature or a special signal). The proposed synthesis method is based on a formal Boolean representation of corresponding functions. Its main advantage can be recognized in strictly rigid and algorithmic notation with the employment of minimization techniques, which is in a direct contrast to competitive solutions, predominantly based on heuristic approaches.

BibTex


@inproceedings{BUT119829,
  author="Adam {Crha} and Richard {Růžička} and Václav {Šimek}",
  title="Synthesis Methodology of Polymorphic Circuits Using Polymorphic NAND/NOR Gates",
  annote="In this paper, a novel approach dealing with the issues of multifunctional
(polymorphic) logic circuits synthesis is presented. Crucial notion behind the
polymorphic concept resides in the fact that such kind of circuit is able to
perform more than one logic function, while the underlying structure
keeps its arrangement untouched. The outlined behaviour is established by means
of utilizing special multifunctional components (gates) during circuit design
phase, where the individual connections among them remains unchanged (no
reconfiguration takes place). The exact function, which the circuit is purposely
executing at a given moment, is determined by the actual operating environment
(e.g. supply voltage, temperature or a special signal). The proposed synthesis
method is based on a formal Boolean representation of corresponding
functions. Its main advantage can be recognized in strictly rigid and algorithmic
notation with the employment of minimization techniques, which is in a direct
contrast to competitive solutions, predominantly based on heuristic approaches.",
  address="IEEE Computer Society",
  booktitle="Proceedings on UKSim-AMSS 17th International Conference on Computer Modelling ans Simulation",
  chapter="119829",
  doi="10.1109/UKSim.2015.82",
  edition="NEUVEDEN",
  howpublished="online",
  institution="IEEE Computer Society",
  year="2015",
  month="march",
  pages="612--617",
  publisher="IEEE Computer Society",
  type="conference paper"
}