Detail publikace

Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors

CHARVÁT, L. SMRČKA, A. VOJNAR, T.

Originální název

Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors

Anglický název

Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors

Jazyk

en

Originální abstrakt

Implementation of a pipeline-based execution of instructions in purpose-specific microprocessors is an error prone task, which implies a need of proper verification of the resulting design. Various techniques were proposed for this purpose, but they usually require a significant manual intervention of the developers. In this work, we propose a novel, highly automated approach for discovering RAW hazards in in-order pipelined instruction execution. Our approach combines static analysis of data paths to detect anomalies and possible hazards, followed by a transformation of detected problematic paths to a parameterised system, and a subsequent formal verification to check the possibility of unhandled hazards using techniques for formal verification of parameterised systems. We have implemented our approach and successfully applied it on multiple non-trivial microprocessors.

Anglický abstrakt

Implementation of a pipeline-based execution of instructions in purpose-specific microprocessors is an error prone task, which implies a need of proper verification of the resulting design. Various techniques were proposed for this purpose, but they usually require a significant manual intervention of the developers. In this work, we propose a novel, highly automated approach for discovering RAW hazards in in-order pipelined instruction execution. Our approach combines static analysis of data paths to detect anomalies and possible hazards, followed by a transformation of detected problematic paths to a parameterised system, and a subsequent formal verification to check the possibility of unhandled hazards using techniques for formal verification of parameterised systems. We have implemented our approach and successfully applied it on multiple non-trivial microprocessors.

Dokumenty

BibTex


@inproceedings{BUT119794,
  author="Lukáš {Charvát} and Aleš {Smrčka} and Tomáš {Vojnar}",
  title="Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors",
  annote="
Implementation of a pipeline-based execution of instructions in purpose-specific
microprocessors is an error prone task, which implies a need of proper
verification of the resulting design. Various techniques were proposed for this
purpose, but they usually require a significant manual intervention of the
developers. In this work, we propose a novel, highly automated approach for
discovering RAW hazards in in-order pipelined instruction execution. Our approach
combines static analysis of data paths to detect anomalies and possible hazards,
followed by a transformation of detected problematic paths to a parameterised
system, and a subsequent formal verification to check the possibility of
unhandled hazards using techniques for formal verification of parameterised
systems. We have implemented our approach and successfully applied it on multiple
non-trivial microprocessors.",
  address="IEEE Computer Society",
  booktitle="Proceedings of 15th International Workshop on Microprocessor Test and Verification (MTV 2014)",
  chapter="119794",
  doi="10.1109/MTV.2014.21",
  edition="NEUVEDEN",
  howpublished="online",
  institution="IEEE Computer Society",
  year="2014",
  month="december",
  pages="83--89",
  publisher="IEEE Computer Society",
  type="conference paper"
}