Detail publikace

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Originální název

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Anglický název

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Jazyk

en

Originální abstrakt

Field programmable gate arrays can be considered to be the most popular and successful platform for evolvable hardware. They allow to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all programmable system-on-chip. The proposed architecture offers high flexibility by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast candidate evaluation. The proposed architecture is evaluated by evolutionary design of switching image filters. The experimental results demonstrate superiority over the previous approaches considering the time required for evolution, area overhead, and flexibility.

Anglický abstrakt

Field programmable gate arrays can be considered to be the most popular and successful platform for evolvable hardware. They allow to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all programmable system-on-chip. The proposed architecture offers high flexibility by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast candidate evaluation. The proposed architecture is evaluated by evolutionary design of switching image filters. The experimental results demonstrate superiority over the previous approaches considering the time required for evolution, area overhead, and flexibility.

BibTex


@article{BUT119780,
  author="Roland {Dobai} and Lukáš {Sekanina}",
  title="Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware",
  annote="
Field programmable gate arrays can be considered to be the most popular and
successful platform for evolvable hardware. They allow to establish and later
reconfigure candidate solutions. Recent work in the field of evolvable hardware
includes the use of virtual and native reconfigurations. Both of these approaches
have their disadvantages. The virtual reconfiguration is characterized by lower
maximal operational frequency of the resulting solutions, and the native
reconfiguration is slower. In this work, a hybrid approach is used merging the
advantages while limiting the disadvantages of the virtual and native
reconfigurations. The main contribution is the new low-level architecture for
evolvable hardware in the new Zynq-7000 all programmable system-on-chip. The
proposed architecture offers high flexibility by considering direct modification
of the reconfigurable resources. The impact of the higher reconfiguration time of
the native approach is limited by the dense placement of the proposed
reconfigurable processing elements. These processing elements also ensure fast
candidate evaluation. The proposed architecture is evaluated by evolutionary
design of switching image filters. The experimental results demonstrate
superiority over the previous approaches considering the time required for
evolution, area overhead, and flexibility.",
  address="NEUVEDEN",
  chapter="119780",
  doi="10.1145/2700414",
  edition="NEUVEDEN",
  howpublished="print",
  institution="NEUVEDEN",
  number="3",
  volume="8",
  year="2015",
  month="may",
  pages="1--24",
  publisher="NEUVEDEN",
  type="journal article in Web of Science"
}