Detail publikace

Fast Simulation of Pipeline in ASIP simulators

Originální název

Fast Simulation of Pipeline in ASIP simulators

Anglický název

Fast Simulation of Pipeline in ASIP simulators

Jazyk

en

Originální abstrakt

A fast and accurate simulator of the newly designed application specific instruction-set processors is essential during processor development, testing, and verification as well as for software development. Instruction-set simulators are usually used at the early stages of the design. They have good performance, but because of their low accuracy they cannot be used for a detailed pipeline or timing analysis. For this task, cycle-accurate simulators are used. They are of high accuracy since the whole microarchitecture is simulated. But at the same time, the simulation time can be significantly longer than in the case of instruction-set simulators. We present a technique which reduces the simulation time with an acceleration of pipeline simulation. Experimental results show a speed-up during simulation. Moreover, the proposed concept can also be used for hardware realization of application specific instruction-set processors.

Anglický abstrakt

A fast and accurate simulator of the newly designed application specific instruction-set processors is essential during processor development, testing, and verification as well as for software development. Instruction-set simulators are usually used at the early stages of the design. They have good performance, but because of their low accuracy they cannot be used for a detailed pipeline or timing analysis. For this task, cycle-accurate simulators are used. They are of high accuracy since the whole microarchitecture is simulated. But at the same time, the simulation time can be significantly longer than in the case of instruction-set simulators. We present a technique which reduces the simulation time with an acceleration of pipeline simulation. Experimental results show a speed-up during simulation. Moreover, the proposed concept can also be used for hardware realization of application specific instruction-set processors.

BibTex


@inproceedings{BUT111785,
  author="Zdeněk {Přikryl}",
  title="Fast Simulation of Pipeline in ASIP simulators",
  annote="A fast and accurate simulator of the newly designed application specific
instruction-set processors is essential during processor development, testing,
and verification as well as for software development. Instruction-set simulators
are usually used at the early stages of the design. They have good performance,
but because of their low accuracy they cannot be used for a detailed pipeline or
timing analysis. For this task, cycle-accurate simulators are used. They are of
high accuracy since the whole microarchitecture is simulated. But at the same
time, the simulation time can be significantly longer than in the case of
instruction-set simulators. We present a technique which reduces the simulation
time with an acceleration of pipeline simulation. Experimental results show
a speed-up during simulation. Moreover, the proposed concept can also be used for
hardware realization of application specific instruction-set processors.",
  address="IEEE Computer Society",
  booktitle="15th International Workshop on Microprocessor Test and Verification",
  chapter="111785",
  doi="10.1109/MTV.2014.18",
  edition="NEUVEDEN",
  howpublished="online",
  institution="IEEE Computer Society",
  year="2014",
  month="december",
  pages="1--6",
  publisher="IEEE Computer Society",
  type="conference paper"
}