Detail publikace

Automatic Construction of On-line Checking Circuits Based on Finite Automata

MATUŠOVÁ, L. KAŠTIL, J. KOTÁSEK, Z.

Originální název

Automatic Construction of On-line Checking Circuits Based on Finite Automata

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

In this paper, the approach to the automatic development of checking circuits for unit implemented in FPGA is described. The checking circuit, also denoted as online checker, introduces fault tolerance aspects to the unit. It provides the information about correctness of the unit output. Checkers are constructed from models inferred by active automata learning which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. A platform for automatic construction of online checkers has been designed and implemented. The experimental part of the paper proves that it is possible to automatically generate the model for the online checker which describes the basic behaviour of the checked component. The obtained checker is up to six times smaller than the original component.

Klíčová slova

Fault Tolerant,Active Automata Learning,Online Checkers,Mealy Machine

Autoři

MATUŠOVÁ, L.; KAŠTIL, J.; KOTÁSEK, Z.

Rok RIV

2014

Vydáno

27. 8. 2014

Nakladatel

IEEE Computer Society

Místo

Verona

ISBN

978-0-7695-5074-9

Kniha

17th Euromicro Conference on Digital Systems Design

Strany od

326

Strany do

332

Strany počet

7

BibTex

@inproceedings{BUT111659,
  author="Lucie {Matušová} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Automatic Construction of On-line Checking Circuits Based on Finite Automata",
  booktitle="17th Euromicro Conference on Digital Systems Design",
  year="2014",
  pages="326--332",
  publisher="IEEE Computer Society",
  address="Verona",
  doi="10.1109/DSD.2014.78",
  isbn="978-0-7695-5074-9"
}