Detail publikace

State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

SZURMAN, K. MIČULKA, L. KOTÁSEK, Z.

Originální název

State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

Anglický název

State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

Jazyk

en

Originální abstrakt

The paper is focused on the state synchronization issue for a fault-tolerant systems implemented into SRAM-based FPGA after repairing of detected failure. Fault-tolerant systems often use HW redundancy to increase their reliability and partial dynamic reconfiguration of FPGA to repair the part of configuration memory with copy of the protected circuit where the failure was detected. In the paper, implemented fault-tolerant system which integrates previously developed reconfiguration controller and CAN bus control system is described. Then, generic architecture for the synchronization is proposed and synchronization methods for given fault-tolerant system are implemented.

Anglický abstrakt

The paper is focused on the state synchronization issue for a fault-tolerant systems implemented into SRAM-based FPGA after repairing of detected failure. Fault-tolerant systems often use HW redundancy to increase their reliability and partial dynamic reconfiguration of FPGA to repair the part of configuration memory with copy of the protected circuit where the failure was detected. In the paper, implemented fault-tolerant system which integrates previously developed reconfiguration controller and CAN bus control system is described. Then, generic architecture for the synchronization is proposed and synchronization methods for given fault-tolerant system are implemented.

Dokumenty

BibTex


@inproceedings{BUT111642,
  author="Karel {Szurman} and Lukáš {Mičulka} and Zdeněk {Kotásek}",
  title="State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System",
  annote="The paper is focused on the state synchronization issue for a fault-tolerant
systems implemented into SRAM-based FPGA after repairing of detected failure.
Fault-tolerant systems often use HW redundancy to increase their reliability and
partial dynamic reconfiguration of FPGA to repair the part of configuration
memory with copy of the protected circuit where the failure was detected. In the
paper, implemented fault-tolerant system which integrates previously developed
reconfiguration controller and CAN bus control system is described. Then, generic
architecture for the synchronization is proposed and synchronization methods for
given fault-tolerant system are implemented.",
  address="IEEE Computer Society",
  booktitle="17th Euromicro Conference on Digital Systems Design",
  chapter="111642",
  doi="10.1109/DSD.2014.103",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2014",
  month="august",
  pages="704--707",
  publisher="IEEE Computer Society",
  type="conference paper"
}