Detail publikace

Design Methodology of Configurable High Performance Packet Parser for FPGA

PUŠ, V. KEKELY, L. KOŘENEK, J.

Originální název

Design Methodology of Configurable High Performance Packet Parser for FPGA

Anglický název

Design Methodology of Configurable High Performance Packet Parser for FPGA

Jazyk

en

Originální abstrakt

Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

Anglický abstrakt

Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

Dokumenty

BibTex


@inproceedings{BUT111580,
  author="Viktor {Puš} and Lukáš {Kekely} and Jan {Kořenek}",
  title="Design Methodology of Configurable High Performance Packet Parser for FPGA",
  annote="Packet parsing is among basic operations that are performed at all points of
a network infrastructure. Modern networks impose challenging requirements on the
performance and configurability of packet parsing modules. However, high-speed
parsers often use a significant amount of hardware resources. We propose a novel
architecture of a pipelined packet parser for FPGA, which offers low latency in
addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput
and chip area can be finely tuned to fit the needs of a particular application.
The parser is hand-optimized thanks to a direct implementation in VHDL, yet the
structure is uniform and easily extensible for new protocols.",
  address="IEEE Computer Society",
  booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  chapter="111580",
  doi="10.1109/DDECS.2014.6868788",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2014",
  month="april",
  pages="189--194",
  publisher="IEEE Computer Society",
  type="conference paper"
}