Detail publikace

On NFA-Split Architecture Optimizations

Originální název

On NFA-Split Architecture Optimizations

Anglický název

On NFA-Split Architecture Optimizations

Jazyk

en

Originální abstrakt

The NFA-Split architecture is an efficient approach to the mapping of regular expressions to the FPGA. However, the NFA-Split architecture has some drawbacks. The most significant are the high time complexity due to usage of determinisation to detect simultaneously active states. The other one is in some cases high consumption of BRAMs. The paper presents solutions of those drawbacks. According to the results up to 39 times overall speedup of  construction of the NFA-Split architecture was achieved. Reduction of utilized BRAMs is up to 97%.

Anglický abstrakt

The NFA-Split architecture is an efficient approach to the mapping of regular expressions to the FPGA. However, the NFA-Split architecture has some drawbacks. The most significant are the high time complexity due to usage of determinisation to detect simultaneously active states. The other one is in some cases high consumption of BRAMs. The paper presents solutions of those drawbacks. According to the results up to 39 times overall speedup of  construction of the NFA-Split architecture was achieved. Reduction of utilized BRAMs is up to 97%.

BibTex


@inproceedings{BUT111523,
  author="Vlastimil {Košař} and Jan {Kořenek}",
  title="On NFA-Split Architecture Optimizations",
  annote="The NFA-Split architecture is an efficient approach to the mapping of regular
expressions to the FPGA. However, the NFA-Split architecture has some drawbacks.
The most significant are the high time complexity due to usage of determinisation
to detect simultaneously active states. The other one is in some cases high
consumption of BRAMs. The paper presents solutions of those drawbacks. According
to the results up to 39 times overall speedup of  construction of the NFA-Split
architecture was achieved. Reduction of utilized BRAMs is up to 97%.",
  address="IEEE Computer Society",
  booktitle="2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)",
  chapter="111523",
  doi="10.1109/DDECS.2014.6868808",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2014",
  month="april",
  pages="274--277",
  publisher="IEEE Computer Society",
  type="conference paper"
}