Detail publikace

Communication Architectures for Application-Specific Multiprocessor Systems (on a Chip)

Originální název

Communication Architectures for Application-Specific Multiprocessor Systems (on a Chip)

Anglický název

Communication Architectures for Application-Specific Multiprocessor Systems (on a Chip)

Jazyk

en

Originální abstrakt

A problem of designing communication architecture optimized for specific applications is considered. Given the mapping of a parallel algorithm to a homogenous network of CPUs with satisfactory load balancing, all that matters in obtaining the highest performance is the interconnection network and communication algorithms. Several on-chip communication architectures are compared with respect to their performance in group communications and hardware cost. A methodology for designing efficient on-chip interconnects for regular group communication patterns is then suggested. Three benchmark applications are used to illustrate the approach as well as superiority of  the fat cube over the Octagonal architecture.   

Anglický abstrakt

A problem of designing communication architecture optimized for specific applications is considered. Given the mapping of a parallel algorithm to a homogenous network of CPUs with satisfactory load balancing, all that matters in obtaining the highest performance is the interconnection network and communication algorithms. Several on-chip communication architectures are compared with respect to their performance in group communications and hardware cost. A methodology for designing efficient on-chip interconnects for regular group communication patterns is then suggested. Three benchmark applications are used to illustrate the approach as well as superiority of  the fat cube over the Octagonal architecture.   

BibTex


@inproceedings{BUT10900,
  author="Václav {Dvořák}",
  title="Communication Architectures for Application-Specific Multiprocessor Systems (on a Chip)",
  annote="A problem of designing communication architecture optimized for specific applications is considered. Given the mapping of a parallel algorithm to a homogenous network of CPUs with satisfactory load balancing, all that matters in obtaining the highest performance is the interconnection network and communication algorithms. Several on-chip communication architectures are compared with respect to their performance in group communications and hardware cost. A methodology for designing efficient on-chip interconnects for regular group communication patterns is then suggested. Three benchmark applications are used to illustrate the approach as well as superiority of  the fat cube over the Octagonal architecture.   ",
  address="Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture",
  booktitle="Proc. of the 11th International Conference on Software, Telecommunications and Computer Networks SoftCOM 2003",
  chapter="10900",
  institution="Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture",
  year="2003",
  month="october",
  pages="778--782",
  publisher="Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture",
  type="conference paper"
}