Detail publikace

Hardware Architecture for the Fast Pattern Matching

Originální název

Hardware Architecture for the Fast Pattern Matching

Anglický název

Hardware Architecture for the Fast Pattern Matching

Jazyk

en

Originální abstrakt

As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.

Anglický abstrakt

As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.

BibTex


@inproceedings{BUT103447,
  author="Jan {Kaštil} and Vlastimil {Košař} and Jan {Kořenek}",
  title="Hardware Architecture for the Fast Pattern Matching",
  annote="As the speed of current computer networks in-
creases, it is necessary to protect networks by security systems
such as firewalls and Intrusion Detection Systems (IDS) operating
at multigigabit speeds. As attacks on modern networks became
more and more complex, it is necessity to detect attack placed
not only in single packet but at the level of network flows. Pattern
matching in the network flows is the time-critical operation
of many modern IDS. Most of the regularly used patterns
are described by the regular expression. This work describes
advanced hardware architecture for the fast regular expression
matching based on the perfect hashing. The proposed architecture
is scalable and can achieve multigigabit throughput per network
flow.",
  address="IEEE Computer Society",
  booktitle="2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)",
  chapter="103447",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2013",
  month="april",
  pages="120--123",
  publisher="IEEE Computer Society",
  type="conference paper"
}