Detail publikace

Approximate Circuit Design by Means of Evolvable Hardware

Originální název

Approximate Circuit Design by Means of Evolvable Hardware

Anglický název

Approximate Circuit Design by Means of Evolvable Hardware

Jazyk

en

Originální abstrakt

This paper deals with evolutionary design of approximate circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.

Anglický abstrakt

This paper deals with evolutionary design of approximate circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.

BibTex


@inproceedings{BUT103438,
  author="Lukáš {Sekanina} and Zdeněk {Vašíček}",
  title="Approximate Circuit Design by Means of Evolvable Hardware",
  annote="
This paper deals with evolutionary design of approximate
circuits. This class of circuits is characterized by relaxing the requirement on
functional equivalence between the specification and implementation in order to
reduce the area on a chip or minimize energy consumption. We proposed a CGP-based
automated design method which enables to find a good trade off between key
circuit parameters (functionality, area and power consumption). In particular,
the digital approximate circuits consisting of elementary gates are addressed in
this paper. Experimental results are provided for combinational single-output
circuits and adders where two different metrics are compared for the error
assessment.",
  address="IEEE Computer Society",
  booktitle="2013 IEEE International Conference on Evolvable Systems (ICES)",
  chapter="103438",
  doi="10.1109/ICES.2013.6613278",
  edition="Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)",
  howpublished="electronic, physical medium",
  institution="IEEE Computer Society",
  year="2013",
  month="april",
  pages="21--28",
  publisher="IEEE Computer Society",
  type="conference paper"
}