Detail publikace

The FPGA Implementation of Dictionary; HW Consumption Versus Latency

ŠTOHANZL, M. FEDRA, Z.

Originální název

The FPGA Implementation of Dictionary; HW Consumption Versus Latency

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper presents a study on the possibilities of dictionary implementation for a dictionary compression system in FPGA. The possibilities of creation of the dictionary using the registers and the RAM memory are described. For these implementations, the interdependence of hardware consumption and latency during basic dictionary processes like writing, reading and searching a match is described. With regard to the hardware consumption, RAM dictionary implementation is the most effective. On the contrary, dictionary implementation by the registers is more suitable with regard to the latency during searching the matches in the dictionary. For these reasons, the combination of both implementation approaches was implemented. The core of the dictionary is in RAM memory and the searching part is implemented by the registers. This part is similar to a hash table. It is implemented by the parallel shift registers to minimize the searching latency.

Klíčová slova

compression, dictionary, Field Programmable Gate Array (FPGA), hash

Autoři

ŠTOHANZL, M.; FEDRA, Z.

Rok RIV

2013

Vydáno

2. 7. 2013

ISBN

978-1-4799-0403-7

Kniha

Proceedings of The 36th International Conference on Telecommunications and Signal Processing

Strany od

82

Strany do

86

Strany počet

4

BibTex

@inproceedings{BUT100448,
  author="Milan {Štohanzl} and Zbyněk {Fedra}",
  title="The FPGA Implementation of Dictionary; HW Consumption Versus Latency",
  booktitle="Proceedings of The 36th International Conference on Telecommunications and Signal Processing",
  year="2013",
  pages="82--86",
  isbn="978-1-4799-0403-7"
}