Detail publikace

The FPGA Implementation of Dictionary; HW Consumption Versus Latency

ŠTOHANZL, M. FEDRA, Z.

Originální název

The FPGA Implementation of Dictionary; HW Consumption Versus Latency

Anglický název

The FPGA Implementation of Dictionary; HW Consumption Versus Latency

Jazyk

en

Originální abstrakt

This paper presents a study on the possibilities of dictionary implementation for a dictionary compression system in FPGA. The possibilities of creation of the dictionary using the registers and the RAM memory are described. For these implementations, the interdependence of hardware consumption and latency during basic dictionary processes like writing, reading and searching a match is described. With regard to the hardware consumption, RAM dictionary implementation is the most effective. On the contrary, dictionary implementation by the registers is more suitable with regard to the latency during searching the matches in the dictionary. For these reasons, the combination of both implementation approaches was implemented. The core of the dictionary is in RAM memory and the searching part is implemented by the registers. This part is similar to a hash table. It is implemented by the parallel shift registers to minimize the searching latency.

Anglický abstrakt

This paper presents a study on the possibilities of dictionary implementation for a dictionary compression system in FPGA. The possibilities of creation of the dictionary using the registers and the RAM memory are described. For these implementations, the interdependence of hardware consumption and latency during basic dictionary processes like writing, reading and searching a match is described. With regard to the hardware consumption, RAM dictionary implementation is the most effective. On the contrary, dictionary implementation by the registers is more suitable with regard to the latency during searching the matches in the dictionary. For these reasons, the combination of both implementation approaches was implemented. The core of the dictionary is in RAM memory and the searching part is implemented by the registers. This part is similar to a hash table. It is implemented by the parallel shift registers to minimize the searching latency.

Dokumenty

BibTex


@inproceedings{BUT100448,
  author="Milan {Štohanzl} and Zbyněk {Fedra}",
  title="The FPGA Implementation of Dictionary; HW Consumption Versus Latency",
  annote="This paper presents a study on the possibilities of
dictionary implementation for a dictionary compression system
in FPGA. The possibilities of creation of the dictionary using the
registers and the RAM memory are described. For these implementations,
the interdependence of hardware consumption and
latency during basic dictionary processes like writing, reading
and searching a match is described. With regard to the hardware
consumption, RAM dictionary implementation is the most effective.
On the contrary, dictionary implementation by the registers
is more suitable with regard to the latency during searching the
matches in the dictionary. For these reasons, the combination
of both implementation approaches was implemented. The core
of the dictionary is in RAM memory and the searching part is
implemented by the registers. This part is similar to a hash table.
It is implemented by the parallel shift registers to minimize the
searching latency.",
  booktitle="Proceedings of The 36th International Conference on Telecommunications and Signal Processing",
  chapter="100448",
  howpublished="electronic, physical medium",
  year="2013",
  month="july",
  pages="82--86",
  type="conference paper"
}