Ing.

Jiří Matyáš

FIT, UITS

imatyas@fit.vutbr.cz

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Ing. Jiří Matyáš

Publikace

  • 2018

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. ADAC: Automated Design of Approximate Circuits. In Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018. s. 612-620. ISBN: 978-3-319-96145-3.
    Detail | WWW

  • 2017

    ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017. s. 416-423. ISBN: 978-1-5386-3093-8.
    Detail | WWW

*) Citace publikací se generují jednou za 24 hodin.