Course detail

VHDL Seminar

FIT-IVHAcad. year: 2020/2021

Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.

Learning outcomes of the course unit

The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioural and structural description. This course is recommended as a co-requisite for INC and INP.


Basic skills in programming and digital design, fundamentals of Boolean algebra.


Not applicable.

Recommended optional programme components

Not applicable.

Recommended or required reading

Lecture notes.
Lecture materials in electronic form. (EN)
FITkit web pages: (EN)
FITkit web pages:
Jasinski, R.: Effective Coding with VHDL: Principles and Best Practice. The MIT Press. 2016.
Pedroni, V. A.: Circuit Design and Simulation with VHDL (Second Edition). The MIT Press. 2011
Armstrong, J.R. - Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
Chang, K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997
Armstrong, J.R. - Gray F.G.: Structured Logic Design with VHDL, Prentice-Hall, 1993

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Project supported by the written technical report in the English language.
Exam prerequisites:
Class credit is gained when a minimum total score of 50% points is gained during a semester.

Language of instruction

Czech, English

Work placements

Not applicable.


To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.

Classification of course in study plans

  • Programme BIT Bachelor's, 1. year of study, summer semester, 4 credits, compulsory-optional

  • Programme IT-BC-3 Bachelor's

    branch BIT , 1. year of study, summer semester, 4 credits, compulsory-optional

  • Programme BIT Bachelor's, 2. year of study, summer semester, 4 credits, compulsory-optional

  • Programme IT-BC-3 Bachelor's

    branch BIT , 2. year of study, summer semester, 4 credits, compulsory-optional

Type of course unit



26 hours, optionally

Teacher / Lecturer


  1. Modern hardware design (design flow), hardware description languages (VHDL, Verilog), FPGA, introduction to digital systems.
  2. Basic VHDL language structure, lexical description, VHDL source code.
  3. Data types, data objects, object classes, data object declaration.
  4. VHDL language statements
  5. Advanced VHDL language properties, time delay and scheduling.
  6. Combination circuits description, three-state circuits.
  7. Synchronous sequential circuits description, finite state automata description, asynchronous sequential circuits.
  8. Circuits modeling and event based simulation, circuit testing, test design, functional simulation (ModelSIM), co-simulation.
  9. Circuit synthesis, constraints, synthesis for FPGA, time simulation.
  10. Advanced methods (pipelining, retiming, component sharing, flattening and structuring)
  11. Complex circuit case study: LED matrix display, UART, ETHERNET
  12. Complex circuit case study: RISC processor
  13. FPGA circuits, mass parallelism in cryptography (RC4, DES), DNA-alignment


13 hours, compulsory

Teacher / Lecturer


Individual project dividend into several parts.