Course detail

Digital Systems Design (in English)

FIT-INCeAcad. year: 2020/2021

Binary digit system: Positional notation, conversion of base, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: Logic expressions, reduction methods, design of combinational logic networks. Analysis of logic networks behaviour: Signal races, hazards. Selected logic modules: Adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Sequential logic networks, latches and flip-flops. State machines and their representations. Design of synchronized sequential networks: State assigment, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital equipment, design strategy. Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: Gate arrays, PROM, PLA, PAL. Simple asynchronous networks: Design, analysis of behaviour, hazards.

Nabízen zahradničním studentům

Všech fakult

Learning outcomes of the course unit

A practical use of selected methods for specification of combinational and sequential logic networks. An encompassment of analysis and design of simple combinational and sequential networks. An encompassment of analysis and design of simple digital equipments using combinational and sequential circuits and blocks.

Prerequisites

The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.

Co-requisites

Not applicable.

Recommended optional programme components

Not applicable.

Recommended or required reading

Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS (http://www.wkap.nl/prod/b/0-7923-8456-3). Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I (http://www.cs.ualberta.ca/~amaral/courses/229/). University of Alberta, Edmonton, CA, 2003.
Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II (http://www.cs.ualberta.ca/~amaral/courses/329/). University of Alberta, Edmonton, CA, 2003.
Eysselt, M.: Digital Systems Design: Basic Set of Problems 1 (http://www.fit.vutbr.cz/research/view_pub.php.en?id=7130) (SSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version (http://www.fit.vutbr.cz/~eysselt/inc/inc-1se1.htm)).
Eysselt, M.: Digital Systems Design: Basic Set of Problems 2 (http://www.fit.vutbr.cz/research/view_pub.php?id=7140) (MSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version (http://www.fit.vutbr.cz/~eysselt/inc/inc-2se1.htm)).
Eysselt, M.: Digital Systems Design: Binary Logic Elements (http://www.fit.vutbr.cz/research/view_pub.php.en?id=7132) (Grafic Symbols for Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version (http://www.fit.vutbr.cz/~eysselt/inc/inc-bsy1.htm)).
Eysselt, M.: Digital Systems Design: Laboratory (http://www.fit.vutbr.cz/research/view_pub.php.en?id=7131) (TTL Family Circuits and Functional Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version (http://www.fit.vutbr.cz/~eysselt/inc/inc-lab1.htm)).
Eysselt, M.: Digital Systems Design: Slides 2003 (http://www.fit.vutbr.cz/research/view_pub.php.en?id=7133) (Set of Basic Slides). Student-Text of the FIT, Brno UT, 2003.
Eysselt, M.: Digital Systems Design: Programmable Logic Devices (http://www.fit.vutbr.cz/research/view_pub.php.en?id=7088) (Foundations & Examples). Student-Text of the FIT Brno UT, FIT Brno UT, 2003 (WWW version (http://www.fit.vutbr.cz/~eysselt/inc/inc-pld1.htm)).
McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
Katz, R.H.: Contemporary Logic Design. Addison-Wesley/Benjamin-Cummings Publishing CO, Redwood City, CA, USA, ISBN 0-8053-2703-7, 1993.
Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

  • Stop and Check Test: 20 points.
  • Mid-Semester Exam: 20 points.
  • Final Exam: 60 points.
    Passing bounary for ECTS assessment: 50 points.

  • Exam prerequisites:
    Requirements for class accreditation are not defined.

    Language of instruction

    English

    Work placements

    Not applicable.

    Aims

    To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. To learn about design of digital circuits consisting of combinational and sequential logic devices.

    Specification of controlled education, way of implementation and compensation for absences

    Test, mid-term exam and final exam are the monitored, and points earning, education. Test and mid-term exam are without correction eventuality. Final exam has two additional correction eventualities.

    Classification of course in study plans

    • Programme IT-BC-1H Bachelor's

      branch BCH , any year of study, winter semester, 5 credits, recommended

    Type of course unit

     

    Lecture

    39 hours, optionally

    Teacher / Lecturer

    Syllabus


    • Binary digit system: Positional notation, conversion of base, binary codes, binary arithmetic.
    • Boolean algebra, logic functions and their representations, logic expressions.
    • Reduction methods: Qiune-McCluskey tabular method, Petrick's cover function.
    • Reduction methods: Karnaugh maps, logic and functional diagrams.
    • Analysis of logic networks behaviour: Signal races, hazards.
    • Selected logic modules: Adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit.
    • Sequential logic networks, latches and flip-flops.
    • State machines and their representations. Design of synchronized sequential networks: State assigment, optimization and implementation. Register, counter, shift register, impulse divider.
    • Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: Gate arrays, PROM, PLA, PAL.
    • Simple asynchronous networks: Design, analysis of behaviour, hazards.

    Fundamentals seminar

    13 hours, compulsory

    Teacher / Lecturer

    Syllabus


    • Binary digit system: Positional notation, conversion of base, binary codes, binary arithmetic.
    • Boolean algebra, logic functions and their representations, a behaviour analysis of contact-switch networks.
    • Logic expressions. Qiune-McCluskey tabular reduction method, Petrick's cover function.
    • Reduction methods: Karnaugh maps, logic and functional diagrams.
    • Logic functions implementation using SSI i.cs. Behaviour analysis of logic networks: Signal races, hazards.
    • Selected logic modules: Adders, subtractor.
    • State machines and their representations. Design of synchronized sequential networks.
    • Design of logic networks based on MSI and LSI i.cs. Programmable logic devices: Gate arrays, PROM, PLA, PAL.

    Exercise in computer lab

    13 hours, compulsory

    Teacher / Lecturer