Programmable Logic Devices
FEKT-NPLDAcad. year: 2019/2020
Students get more detailed knowledge in the area of digital circuits design, especially with respect to their implementation into PLDs (FPGAs, CPLDs) and ASICs. Students get overview of current technology of these integrated circuits, their off-the-shelf architectures, principles of design and application of basic digital subsystems (counters, finite state machines, memory structures). During the PC lectures students get familiar with modern system for FPGA configuration. This includes description of the digital system (using VHDL source codes, schematic, IP cores), its implementation and verification using simulator. After passing the course students are able to design and implement simple digital system into an FPGA (using VHDL language).
Learning outcomes of the course unit
The graduate is able to
o describe simple digital system using VHDL
o verify simple digital system using VHDL
o choose type of finite state machine and give reasons for the choice
o design and implement a finite state machine using VHDL
o compare different architectures of PLDs and choose a proper one for particular application
o specify timing requirements for a design and verify that they are met after implementation
o implement simple IP cores like memories and simple DSP blocks (FIR filtres)
o implement simple microcontroller into FPGA, program it and use in target application
o state requirements on FPGA power supply system
o analyze and prevent/solve basic signal integrity issues
Students are expected to know basic of impulse and digital technology: the Boolean algebra, Karnaugh maps, truth tables, function of basic gates and flip-flops (registers), principle and effect of signal propagation through active and passive transmission elements.
Recommended optional programme components
Recommended or required reading
KUBÍČEK, M.: Úvod do problematiky obvodů FPGA pro integrovanou výuku VUT a VŠB-TUO. [Skriptum FEKT VUT v Brně.], Ústav telekomunikací FEKT, VUT, Brno 2014, ISBN 978-80-214-5069-1 (CS)
MAXFIELD, C.: The Design Warrior's Guide to FPGAs. Elsevier, 2004 (EN)
SKAHILL, K.: VHDL for Programmable Logic, Addison-Wesley, 1996 (EN)
WAKERLY, J.: Digital Design - principles and practices. 4-th Ed. Pearson Education LTD, Prentice Hall, 2005 (EN)
Planned learning activities and teaching methods
Techning methods include lectures and computer laboratories. Course is taking advantage of e-learning (Moodle) system. The main focus is on computer laboratories with strong emphasis on practical skills.
Assesment methods and criteria linked to learning outcomes
Students obtain points for the activity in computer labs during the semester. The final exam is composed of written, practical and oral part.
Language of instruction
1. Introduction to digital integrated circuits, history and development of CPLDs and FPGAs
2. Introduction to VHDL programming language
3. The basics of digital systems: gates, flip-flops, shift registers, counters
4. Moor and Mealy state machines
5. Practical design and application of finite state machines, microsequencers
6. Basis architecture of FPGAs and CPLDs: logic cells, programmable interconnect, I/O cells
7. Timing of digital circuits, metastability, methods for increasing clock frequency
8. FPGA clock domains, clock enabling, clock management, synchronous and asynchronous reset
9. Memory structures in FPGAs, use of RAM, ROM and FIFO
10. Digital signal processing in FPGAs, dedicated blocks for DSP acceleration
11. Advanced FPGA structural features, HARD and SOFT IP cores, implementation of basic IP cores
12. Processors in FPGA, SoC, FPGA manufacturing technology, FPGA configuration
13. Signal integrity, PCB and power design for FPGA, radiation effects.
Lectures are aimed to teach students the basic principles of modern PLDs, particularly CPLDs and FPGAs, while they will be able not only to configure (program) them, but also select proper device and implement it into a system.
Specification of controlled education, way of implementation and compensation for absences
Evaluation of activities is specified by a regulation, which is issued by the lecturer responsible for the course annually.
Classification of course in study plans
- Programme EEKR-MN Master's
branch MN-TIT , 1. year of study, summer semester, 6 credits, optional interdisciplinary
branch MN-EST , 1. year of study, summer semester, 6 credits, optional specialized
branch MN-MEL , 1. year of study, summer semester, 6 credits, optional interdisciplinary
branch MN-SVE , 1. year of study, summer semester, 6 credits, optional interdisciplinary