Course detail

Logical systems

FEKT-LLOSAcad. year: 2015/2016

Knowledge of the subject Control Electronics (REB) passed by the student in the batchelor studies is presumpted. This subject gives a broader view on logic systems and their theoretical base (e. g. the morelevel logic and its advantages and disadvantages). A set of themes connected with applications of logic systems in control, in steering of measuring systems, in data acquisition and processing as well as the additional problems like the rise and suppression of disturbance will be discussed. To these themes belong also the design of non-standard logic elements and circuits, the problematics of coding and its use for the safety of data tramission and data storing, the use of the large-scale integration circuits like there are the semiconductor memories, programmable logic arrays and their programming and the auxiliary circuits for microprocessors.

Learning outcomes of the course unit

The student reaches a narrow contact with the digital techniques, with its theoretical base and with the technical means of its practical use.

Prerequisites

The subject knowledge on the Bachelor´s degree level is requested.

Co-requisites

Not applicable.

Recommended optional programme components

Not applicable.

Recommended or required reading

Kolouch, J.: Programovatelné logické obvody - Přednášky [Skriptum FEKT VUT v Brně] Brno 2005 (CS)
Kolouch, J.: Programovatelné logické obvody a návrh aplikací v jazycích ABEL a VHDL - počítačové cvičení [Skriptum FEKT VUT v Brně.]Brno 2005 (CS)
Musil, V. a kol.: Navrhování digitálních integrovaných obvodů. Jazyk VHDL [Skriptum FEKT VUT v Brně] Brno 2000 (CS)
Wakerly, J. F.: Digital Design Principles and Practices. Prentice Hall, 2001 (EN)
Xilinx Synthesis Technology User Guide (xst.pdf) Součást dokumentace k návrhovým systémům firmy Xilinx (EN)
4.Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW vydání. (EN)
1.Chang, K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997 (EN)
Pinker, J. Poupa, M: Číslicové systémy a jazyk VHDL. 2006, ISBN 80-730-0195-5

Planned learning activities and teaching methods

Teaching methods include lecture, numeric laboratories and practical laboratories. Student have to write 7 single projects.

Assesment methods and criteria linked to learning outcomes

Requirements for completion of a course are specified by a regulation issued by the lecturer responsible for the course and updated for every.
up to 30 points for the evaluation and laboratory tests.
up to 70 points for the final written examination.

Language of instruction

Czech

Work placements

Not applicable.

Course curriculum

1. Boolean algebra.Reduction methods: Karnaugh maps.
2. Reduction methods: Qiune-McCluskey tabular methodAnalysis of logic networks behaviour, signal races, hazards.
3. Adder, multiplexer, demultiplexer, decoder. Asynchronous networks, latches and flip-flops.
4. Sequential logic networks. State machines and their representations.
5. VHDL Language, Data types, VHDL commands
6. Combination a Sequential circuits, State automats. Testing and functional simulation.

Aims

To enlarge the knowledge of logic circuits from the batchelor studies and to fulfil them by the knowledge of the design, construction, testing and practical use.
To give the students the knowledge of syntax and semantics of hardware description language VHDL
VHDL for modelling, simulation and synthesis complex digital syystems.
Programming techniques in XILINX ISE

Specification of controlled education, way of implementation and compensation for absences

The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.

Classification of course in study plans

  • Programme EEKR-ML Master's

    branch ML-KAM , 1. year of study, winter semester, 6 credits, compulsory

  • Programme EEKR-ML1 Master's

    branch ML1-KAM , 1. year of study, winter semester, 6 credits, compulsory

  • Programme EEKR-CZV lifelong learning

    branch ET-CZV , 1. year of study, winter semester, 6 credits, compulsory

Type of course unit

 

Lecture

39 hours, optionally

Teacher / Lecturer

Exercise

13 hours, compulsory

Teacher / Lecturer

Laboratory exercise

13 hours, compulsory

Teacher / Lecturer