Publication detail

A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology

KLEDROWETZ, V. PAVLÍK, M. HÁZE, J. FUJCIK, L. PROKOP, R.

Original Title

A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology

Czech Title

Návrh 12-bitového sigma-delta modulátoru druhého řádu v technologii CMOS 0,7 um

English Title

A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology

Type

conference paper

Language

en

Original Abstract

The presented work deals with design of the sigma-delta modulator in CMOS I2100 0,7 um technology. This modulator is designed using the switched capacitor technique (SC). For offset compensation of operational amplifiers (opamps) each integrator uses correlated double sampling technique (CDS), which minimize impact of offset of opamps. The sigma-delta modulator is part of the system for signal processing from sensor applications. Requirements for this converter were resolution 12-bits, voltage range 4 V, common mode voltage 2,5 V, +- 2 V input signal amplitude, bandwidth of a processed signal 5 kHz. Second order structure CIDIDF (Cascaded Integrator with Distributed Input and Distributed Feedback) was chosen.

Czech abstract

Předkládaná práce se zabývá návrhem sigma-delta modulátoru v technologii CMOS 0,7 um. Je využito techniky spínaných kapacitorů (SC). Pro potlačení ofsetu operačních zesilovačů je v každém integrátoru kompenzační kapacitor (CDS technika). Tento sigma-delta modulátor je částí systému pro zpracování signálů ze senzorů. Požadavkem bylo rozlišení 12-bitů, napěťový rozsah 4 V, souhlasné napětí 2,5 V, maximální amplituda vstupního signálu +-2 V. Pásmo zpracovávaného signálu je 5 kHz.

English abstract

The presented work deals with design of the sigma-delta modulator in CMOS I2100 0,7 um technology. This modulator is designed using the switched capacitor technique (SC). For offset compensation of operational amplifiers (opamps) each integrator uses correlated double sampling technique (CDS), which minimize impact of offset of opamps. The sigma-delta modulator is part of the system for signal processing from sensor applications. Requirements for this converter were resolution 12-bits, voltage range 4 V, common mode voltage 2,5 V, +- 2 V input signal amplitude, bandwidth of a processed signal 5 kHz. Second order structure CIDIDF (Cascaded Integrator with Distributed Input and Distributed Feedback) was chosen.

Keywords

Sigma-delta modulator, SC technique, CDS technique, operational amplifier

RIV year

2012

Released

28.06.2012

Publisher

VUT Brno

Location

Brno

ISBN

978-80-214-4539-0

Book

IMAPS CS International Conference 2012

Edition

1

Edition number

1

Pages from

208

Pages to

213

Pages count

5

BibTex


@inproceedings{BUT93602,
  author="Vilém {Kledrowetz} and Michal {Pavlík} and Jiří {Háze} and Lukáš {Fujcik} and Roman {Prokop}",
  title="A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology",
  annote="The presented work deals with design of the sigma-delta modulator in CMOS I2100 0,7 um technology. This modulator is designed using the switched capacitor technique (SC). For offset compensation of operational amplifiers (opamps) each integrator uses correlated double sampling technique (CDS), which minimize impact of offset of opamps. The sigma-delta modulator is part of the system for signal processing from sensor applications. Requirements for this converter were resolution 12-bits, voltage range 4 V, common mode voltage 2,5 V, +- 2 V input signal amplitude, bandwidth of a processed signal 5 kHz. Second order structure CIDIDF (Cascaded Integrator with Distributed Input and Distributed Feedback) was chosen.",
  address="VUT Brno",
  booktitle="IMAPS CS International Conference 2012",
  chapter="93602",
  edition="1",
  howpublished="print",
  institution="VUT Brno",
  year="2012",
  month="june",
  pages="208--213",
  publisher="VUT Brno",
  type="conference paper"
}