Publication detail

FPGA-based In-system Jitter Measurement

KUBÍČEK, M. KOLKA, Z.

Original Title

FPGA-based In-system Jitter Measurement

English Title

FPGA-based In-system Jitter Measurement

Type

conference paper

Language

en

Original Abstract

The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acquired using an oscilloscope.

English abstract

The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acquired using an oscilloscope.

Keywords

bit error rate, confidence level, FPGA, jitter

RIV year

2011

Released

23.11.2011

Publisher

Fakulta elektrotechniky, ČVUT

Location

Technická 2, Praha 6, 166 27

ISBN

978-80-01-04887-0

Book

ISMOT Proceedings 2011

Edition

1

Edition number

1

Pages from

277

Pages to

280

Pages count

4

BibTex


@inproceedings{BUT74718,
  author="Michal {Kubíček} and Zdeněk {Kolka}",
  title="FPGA-based In-system Jitter Measurement",
  annote="The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals.
The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources.
The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acquired using an oscilloscope.",
  address="Fakulta elektrotechniky, ČVUT",
  booktitle="ISMOT Proceedings 2011",
  chapter="74718",
  edition="1",
  howpublished="electronic, physical medium",
  institution="Fakulta elektrotechniky, ČVUT",
  year="2011",
  month="november",
  pages="277--280",
  publisher="Fakulta elektrotechniky, ČVUT",
  type="conference paper"
}