Publication detail

Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures

SEKANINA, L. MIKUŠEK, P.

Original Title

Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In this paper we propose three small instances of a reconfigurable circuit and analyze their properties using the brute force method and evolutionary algorithm. Although proposed circuits are very similar, significant differences were demonstrated, namely in the number of unique designs they can implement, the sensitiveness of functions to the inversions in the configuration bitstream and the average number of generations needed to find a target function. These findings are quite unintuitive. Once important (sensitive) bits of the reconfigurable circuit are identified, evolutionary algorithm can incorporate this knowledge. We believe that the proposed type of analysis can help those designers who develop new reconfigurable circuits for evolvable hardware applications.

Keywords

reconfigurable device, digital circuit, evolutionary design

Authors

SEKANINA, L.; MIKUŠEK, P.

RIV year

2008

Released

30. 3. 2008

Publisher

Springer Verlag

Location

Berlin

ISBN

978-3-540-78760-0

Book

Applications of Evolutionary Computing

Edition

Lecture Notes in Computer Science

Pages from

144

Pages to

153

Pages count

10

URL

https://www.fit.vut.cz/research/publication/8591/

BibTex

@inproceedings{BUT34273,
  author="Lukáš {Sekanina} and Petr {Mikušek}",
  title="Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures",
  booktitle="Applications of Evolutionary Computing",
  year="2008",
  series="Lecture Notes in Computer Science",
  volume="4974",
  pages="144--153",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-540-78760-0",
  url="https://www.fit.vut.cz/research/publication/8591/"
}