Publication detail

Synthesis and Design of Floating Inductance Simulators at VHF-Band Using MOS-Only Approach

KARTCI, A. HERENCSÁR, N. CICEKOGLU, O. METIN, B.

Original Title

Synthesis and Design of Floating Inductance Simulators at VHF-Band Using MOS-Only Approach

English Title

Synthesis and Design of Floating Inductance Simulators at VHF-Band Using MOS-Only Approach

Type

conference paper

Language

en

Original Abstract

The design trend in the analog CMOS signal processing technology is towards the MOS-only approach. Using this technique, this work presents three new core topologies realizing floating positive or negative inductance simulators. The positive inductance simulator (PIS) is investigated as both integer- and fractional-order element. For illustration purpose, the behavior of the fractional-order PIS was tested via implementation in RLC ladder prototype of voltage-mode (VM) high-pass filter with various orders; particularly of orders 2, 2.5, and 3. The performance of the integer-order PIS was tested in third-order VM elliptic low-pass filter at very high frequencies. Theoretical results are verified by LTSPICE simulations using BSIM3 1 µm technology transistor parameters.

English abstract

The design trend in the analog CMOS signal processing technology is towards the MOS-only approach. Using this technique, this work presents three new core topologies realizing floating positive or negative inductance simulators. The positive inductance simulator (PIS) is investigated as both integer- and fractional-order element. For illustration purpose, the behavior of the fractional-order PIS was tested via implementation in RLC ladder prototype of voltage-mode (VM) high-pass filter with various orders; particularly of orders 2, 2.5, and 3. The performance of the integer-order PIS was tested in third-order VM elliptic low-pass filter at very high frequencies. Theoretical results are verified by LTSPICE simulations using BSIM3 1 µm technology transistor parameters.

Keywords

analog signal processing, floating inductance simulator, fractional-order element, fractional-order inductor, MOS-only, negative inductance simulator, positive inductance simulator, RLC ladder filter, third-order elliptic low-pass filter

Released

04.08.2019

Location

Dallas, USA

ISBN

978-1-7281-2788-0

Book

Proceedings of the 2019 62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Dallas, USA

Pages from

89

Pages to

92

Pages count

4

Documents

BibTex


@inproceedings{BUT157963,
  author="Aslihan {Kartci} and Norbert {Herencsár} and Oguzhan {Cicekoglu} and Bilgin {Metin}",
  title="Synthesis and Design of Floating Inductance Simulators at VHF-Band Using MOS-Only Approach",
  annote="The design trend in the analog CMOS signal processing technology is towards the MOS-only approach. Using this technique, this work presents three new core topologies realizing floating positive or negative inductance simulators. The positive inductance simulator (PIS) is investigated as both integer- and fractional-order element. For illustration purpose, the behavior of the fractional-order PIS was tested via implementation in RLC ladder prototype of voltage-mode (VM) high-pass filter with various orders; particularly of orders 2, 2.5, and 3. The performance of the integer-order PIS was tested in third-order VM elliptic low-pass filter at very high frequencies. Theoretical results are verified by LTSPICE simulations using BSIM3 1 µm technology transistor parameters.",
  booktitle="Proceedings of the 2019 62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Dallas, USA",
  chapter="157963",
  doi="10.1109/MWSCAS.2019.8885048",
  howpublished="online",
  year="2019",
  month="august",
  pages="89--92",
  type="conference paper"
}