Publication detail

VDIBA-Based Fractional-Order Oscillator Design

KARTCI, A. HERENCSÁR, N. DVOŘÁK, J. VRBA, K.

Original Title

VDIBA-Based Fractional-Order Oscillator Design

English Title

VDIBA-Based Fractional-Order Oscillator Design

Type

conference paper

Language

en

Original Abstract

This paper deals with a voltage-mode integer- and fractional-order oscillator design providing compact and simple CMOS structure. The proposed circuit consists of only one grounded/floating capacitor, one grounded/floating resistor, and one high-performance and versatile active element so-called voltage differencing inverting buffered amplifier (VDIBA), employing only six transistors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The design parameters of the proposed oscillator can be electronically adjusted via change of order of the fractional-order capacitor and/or by means of bias current of the internal transconductance of the VDIBA. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.

English abstract

This paper deals with a voltage-mode integer- and fractional-order oscillator design providing compact and simple CMOS structure. The proposed circuit consists of only one grounded/floating capacitor, one grounded/floating resistor, and one high-performance and versatile active element so-called voltage differencing inverting buffered amplifier (VDIBA), employing only six transistors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The design parameters of the proposed oscillator can be electronically adjusted via change of order of the fractional-order capacitor and/or by means of bias current of the internal transconductance of the VDIBA. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.

Keywords

fractional calculus; fractional-order capacitor; fractional-order oscillator; MOS-RC oscillator; operational transconductance amplifier; voltage differencing inverting buffered amplifier; Valsa structure; VDIBA

Released

01.07.2019

Publisher

IEEE

Location

Budapest, Hungary

ISBN

978-1-7281-1864-2

Book

Proceedings of the 2019 42nd International Conference on Telecommunications and Signal Processing (TSP), Budapest, Hungary

Pages from

744

Pages to

747

Pages count

4

URL

Full text in the Digital Library

BibTex


@inproceedings{BUT157634,
  author="Aslihan {Kartci} and Norbert {Herencsár} and Jan {Dvořák} and Kamil {Vrba}",
  title="VDIBA-Based Fractional-Order Oscillator Design",
  annote="This paper deals with a voltage-mode integer- and fractional-order oscillator design providing compact and simple CMOS structure. The proposed circuit consists of only one grounded/floating capacitor, one grounded/floating resistor, and one high-performance and versatile active element so-called voltage differencing inverting buffered amplifier (VDIBA), employing only six transistors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The design parameters of the proposed oscillator can be electronically adjusted via change of order of the fractional-order capacitor and/or by means of bias current of the internal transconductance of the VDIBA. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.",
  address="IEEE",
  booktitle="Proceedings of the 2019 42nd International Conference on Telecommunications and Signal Processing (TSP), Budapest, Hungary",
  chapter="157634",
  doi="10.1109/TSP.2019.8769104",
  howpublished="online",
  institution="IEEE",
  year="2019",
  month="july",
  pages="744--747",
  publisher="IEEE",
  type="conference paper"
}