Publication detail

A 12-bit, Low Power Switched-Capacitor Pipelined ADC, A Case Study

HÁZE, J. VRBA, R. SKOČDOPOLE, M. FUJCIK, L.

Original Title

A 12-bit, Low Power Switched-Capacitor Pipelined ADC, A Case Study

English Title

A 12-bit, Low Power Switched-Capacitor Pipelined ADC, A Case Study

Type

conference paper

Language

en

Original Abstract

The paper describes a case study of new 12 bit, low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioral modeling regarding low power consumption. The basic blocks topology design is outlined as well. The cancellation techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of opamp etc. is utilized in the design.

English abstract

The paper describes a case study of new 12 bit, low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioral modeling regarding low power consumption. The basic blocks topology design is outlined as well. The cancellation techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of opamp etc. is utilized in the design.

Keywords

Pipelined ADC, switched-capacitor technique, portable application, error correction scheme

RIV year

2004

Released

01.01.2004

Publisher

Czech Republic

Location

Brno

ISBN

80-214-2701-9

Book

Proceedings of 11th International Conference Electronic Devices and Systems EDS 2004

Edition number

1

Pages from

169

Pages to

173

Pages count

5

BibTex


@inproceedings{BUT11374,
  author="Jiří {Háze} and Radimír {Vrba} and Michal {Skočdopole} and Lukáš {Fujcik}",
  title="A 12-bit, Low Power Switched-Capacitor Pipelined ADC, A Case Study",
  annote="The paper describes a case study of new 12 bit, low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioral modeling regarding low power consumption. The basic blocks topology design is outlined as well. The cancellation techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of opamp etc. is utilized in the design.",
  address="Czech Republic",
  booktitle="Proceedings of 11th International Conference Electronic Devices and Systems EDS 2004",
  chapter="11374",
  institution="Czech Republic",
  year="2004",
  month="january",
  pages="169",
  publisher="Czech Republic",
  type="conference paper"
}