Publication detail

Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation

SOVA, V. GREPL, R.

Original Title

Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation

English Title

Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation

Type

conference paper

Language

en

Original Abstract

This paper presents Hardware in the Loop (HIL) simulation of the BLDC motor used in aerospace applications. Due to a high frequency driving signals and a high dynamics of the electrical part of the BLDC motor, the utilization of FPGA is necessary. The algorithm is distributed between the CPU and the FPGA and targeted to dSPACE modular hardware.

English abstract

This paper presents Hardware in the Loop (HIL) simulation of the BLDC motor used in aerospace applications. Due to a high frequency driving signals and a high dynamics of the electrical part of the BLDC motor, the utilization of FPGA is necessary. The algorithm is distributed between the CPU and the FPGA and targeted to dSPACE modular hardware.

Keywords

BLDC, HIL, FPGA

RIV year

2013

Released

09.10.2013

Publisher

Springer International Publishing

Location

Cham, Heidelberg, New York, Dordrecht, London

ISBN

978-3-319-02293-2

Book

Mechatronics 2013: Recent Technological and Scientific Advances

Edition

Mechatronics

Pages from

135

Pages to

142

Pages count

8

Documents

BibTex


@inproceedings{BUT106474,
  author="Václav {Sova} and Robert {Grepl}",
  title="Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation",
  annote="This  paper  presents  Hardware  in  the  Loop  (HIL)  simulation  of  the 
BLDC  motor  used  in   aerospace  applications.  Due  to  a  high  frequency  driving
signals  and  a  high  dynamics  of  the  electrical  part  of  the  BLDC  motor,  the 
utilization of FPGA is necessary. The algorithm  is distributed between the CPU 
and the FPGA and targeted to dSPACE modular hardware.",
  address="Springer International Publishing",
  booktitle="Mechatronics 2013: Recent Technological and Scientific Advances",
  chapter="106474",
  doi="10.1007/978-3-319-02294-9_84",
  edition="Mechatronics",
  howpublished="print",
  institution="Springer International Publishing",
  year="2013",
  month="october",
  pages="135--142",
  publisher="Springer International Publishing",
  type="conference paper"
}