Publication detail

Automated Functional Verification of Application Specific Instruction-set Processors

ZACHARIÁŠOVÁ, M. PŘIKRYL, Z. HRUŠKA, T. KOTÁSEK, Z.

Original Title

Automated Functional Verification of Application Specific Instruction-set Processors

English Title

Automated Functional Verification of Application Specific Instruction-set Processors

Type

journal article - other

Language

en

Original Abstract

Today's highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging as it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and furthermore, it improves the quality of verification itself.

English abstract

Today's highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging as it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and furthermore, it improves the quality of verification itself.

Keywords

Functional Verification OVM Application Specific Instruction-set Processors EDA Tools

RIV year

2013

Released

19.02.2013

Publisher

Springer Verlag

Location

Berlin Heidelberg

ISBN

1868-4238

Periodical

Environmental Software Systems

Year of study

4

Number

403

State

DE

Pages from

128

Pages to

138

Pages count

10

Documents

BibTex


@article{BUT103464,
  author="Marcela {Zachariášová} and Zdeněk {Přikryl} and Tomáš {Hruška} and Zdeněk {Kotásek}",
  title="Automated Functional Verification of Application Specific Instruction-set Processors",
  annote="Today's highly competitive market of consumer electronics is very sensitive to
the time it takes to introduce a new product. However, the ever-growing
complexity of application specific instruction-set processors (ASIPs) which are
inseparable parts of nowadays complex embedded systems makes this task even more
challenging as it is necessary to test and verify significantly bigger portion of
logic, tricky timing behaviour or specific corner cases in a defined time
schedule. As a consequence, the gap between the proposed verification plan and
quality of verification tasks is widening due to this time restriction. One way
how to solve this issue is using faster, efficient and cost-effective methods of
verification. The aim of this paper is to introduce an automated generation of
SystemVerilog verification environments (testbenches) for verification of ASIPs.
Results show that our approach reduces the time and effort needed for
implementation of testbenches significantly and furthermore, it improves the
quality of verification itself.",
  address="Springer Verlag",
  booktitle="Embedded Systems: Design, Analysis and Verification",
  chapter="103464",
  doi="10.1007/978-3-642-38853-8",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Springer Verlag",
  number="403",
  volume="4",
  year="2013",
  month="february",
  pages="128--138",
  publisher="Springer Verlag",
  type="journal article - other"
}