Publication detail

Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

KUTÁLEK, V., DVOŘÁK, V.

Original Title

Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

English Title

Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture

Type

conference paper

Language

en

Original Abstract

Process- and thread-level parallelism is very often exploited in asynchronous processor pipelines for embedded applications, recently on a chip. The paper deals with simulation of pipelines with one or more workers in each pipeline stage. The number of workers can be adjusted to balance execution time of other stages so as to keep efficiency high. Simulation-based prototyping of such pipeline processor farms using Transim tool can account for communication delays, multitasking, data-dependent variations in workload, CPUs with different speeds, etc. Simulation results for a given task divisible to a few subtasks of arbitrary duration are presented as well as a particular example of a power of a matrix.

English abstract

Process- and thread-level parallelism is very often exploited in asynchronous processor pipelines for embedded applications, recently on a chip. The paper deals with simulation of pipelines with one or more workers in each pipeline stage. The number of workers can be adjusted to balance execution time of other stages so as to keep efficiency high. Simulation-based prototyping of such pipeline processor farms using Transim tool can account for communication delays, multitasking, data-dependent variations in workload, CPUs with different speeds, etc. Simulation results for a given task divisible to a few subtasks of arbitrary duration are presented as well as a particular example of a power of a matrix.

Keywords

Multiprocessor SoC, pipeline/farm architecture, performance prediction

RIV year

2002

Released

22.04.2002

Publisher

Faculty of Information Technology BUT

Location

Brno

ISBN

80-214-2094-4

Book

Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop

Pages from

296

Pages to

299

Pages count

4

Documents

BibTex


@inproceedings{BUT9823,
  author="Vladimír {Kutálek} and Václav {Dvořák}",
  title="Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture",
  annote="Process- and thread-level parallelism is very often exploited in
asynchronous processor pipelines for embedded applications, recently on
a chip. The paper deals with simulation of pipelines with one or more
workers in each pipeline stage. The number of workers can be adjusted
to balance execution time of other stages so as to keep efficiency
high. Simulation-based prototyping of such pipeline processor farms
using Transim tool can account for communication delays, multitasking,
data-dependent variations in workload, CPUs with different speeds, etc.
Simulation results for a given task divisible to a few subtasks of
arbitrary duration are presented as well as a particular example of a
power of a matrix.",
  address="Faculty of Information Technology BUT",
  booktitle="Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop",
  chapter="9823",
  institution="Faculty of Information Technology BUT",
  year="2002",
  month="april",
  pages="296--299",
  publisher="Faculty of Information Technology BUT",
  type="conference paper"
}