Publication detail

Terrain Rendering Algorithm Performance Analysis

POLOK, L. BARTOŇ, R. CHUDÝ, P. KRŠEK, P. SMRŽ, P. DITTRICH, P.

Original Title

Terrain Rendering Algorithm Performance Analysis

English Title

Terrain Rendering Algorithm Performance Analysis

Type

conference paper

Language

en

Original Abstract

Nowadays, the flight guidance equipment supplies practically all the information, required for aircraft navigation. Pseudo-realistic terrain visualization is undoubtedly an important part of this information. Although modern graphics processors are able to render realistic terrain at interactive frame rates, in some applications, it is beneficial to use low-power graphics hardware, perhaps from weight or power supply capacity restrictions. These low-power graphics processors typically manifest much lower computational power than conventional hardware, severely limiting the capability of terrain visualization. A novel method for caching terrain tiles is presented in this paper, enabling faster and more detailed terrain rendering, using lighter devices that consume less power. The main focus was on memory and time efficiency on common low-power graphics hardware. The terrain rendering algorithm being employed in our implementation is derived from the seamless patches algorithm. Different aspects of terrain tile swapping were examined in order to devise a simple hardware metric. An efficient tile caching approach was developed, based on this hardware metric, and its performance was evaluated.

English abstract

Nowadays, the flight guidance equipment supplies practically all the information, required for aircraft navigation. Pseudo-realistic terrain visualization is undoubtedly an important part of this information. Although modern graphics processors are able to render realistic terrain at interactive frame rates, in some applications, it is beneficial to use low-power graphics hardware, perhaps from weight or power supply capacity restrictions. These low-power graphics processors typically manifest much lower computational power than conventional hardware, severely limiting the capability of terrain visualization. A novel method for caching terrain tiles is presented in this paper, enabling faster and more detailed terrain rendering, using lighter devices that consume less power. The main focus was on memory and time efficiency on common low-power graphics hardware. The terrain rendering algorithm being employed in our implementation is derived from the seamless patches algorithm. Different aspects of terrain tile swapping were examined in order to devise a simple hardware metric. An efficient tile caching approach was developed, based on this hardware metric, and its performance was evaluated.

Keywords

terrain rendering, tile caching, allocation algorithm, complexity

RIV year

2012

Released

14.10.2012

Publisher

IEEE Computer Society

Location

Williamsburg, VA, USA

ISBN

978-1-4673-1699-6

Book

Proceedings of the 31st Digital Avionics Systems Conference

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

1

Pages to

7

Pages count

7

URL

Documents

BibTex


@inproceedings{BUT97032,
  author="Lukáš {Polok} and Radek {Bartoň} and Peter {Chudý} and Přemysl {Kršek} and Pavel {Smrž} and Petr {Dittrich}",
  title="Terrain Rendering Algorithm Performance Analysis",
  annote="Nowadays, the flight guidance equipment supplies practically all the information,
required for aircraft navigation. Pseudo-realistic terrain visualization is
undoubtedly an important part of this information. Although modern graphics
processors are able to render realistic terrain at interactive frame rates, in
some applications, it is beneficial to use low-power graphics hardware, perhaps
from weight or power supply capacity restrictions. These low-power graphics
processors typically manifest much lower computational power than conventional
hardware, severely limiting the capability of terrain visualization. A novel
method for caching terrain tiles is presented in this paper, enabling faster and
more detailed terrain rendering, using lighter devices that consume less power.
The main focus was on memory and time efficiency on common low-power graphics
hardware. The terrain rendering algorithm being employed in our implementation is
derived from the seamless patches algorithm. Different aspects of terrain tile
swapping were examined in order to devise a simple hardware metric. An efficient
tile caching approach was developed, based on this hardware metric, and its
performance was evaluated.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the 31st Digital Avionics Systems Conference",
  chapter="97032",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2012",
  month="october",
  pages="1--7",
  publisher="IEEE Computer Society",
  type="conference paper"
}