Publication detail

TWO MODULO 2n +/- 1 ADDERS BASED ON PREFIX COMPUTATION

YOUNES, D. ŠTEFFAN, P.

Original Title

TWO MODULO 2n +/- 1 ADDERS BASED ON PREFIX COMPUTATION

English Title

TWO MODULO 2n +/- 1 ADDERS BASED ON PREFIX COMPUTATION

Type

conference paper

Language

en

Original Abstract

Two novel designs of residue number system adders corresponding moduli 2n–1, 2n+1 are presented in this paper. Both designs are based on prefix computation idea, which was inspired from the technique used in carry look-ahead adder (CLA). This prefix computation speeds up the addition-correction process corresponding to each modulo. The proposed modular adders were designed in such a way to be efficiently implemented on Spartan-3 field programmable gate array (FPGA) board. The implementation results showed time, area savings up to 44.7%, 14.3%, respectively, which indicates that these adders are very effective for designs with critical timing requirements.

English abstract

Two novel designs of residue number system adders corresponding moduli 2n–1, 2n+1 are presented in this paper. Both designs are based on prefix computation idea, which was inspired from the technique used in carry look-ahead adder (CLA). This prefix computation speeds up the addition-correction process corresponding to each modulo. The proposed modular adders were designed in such a way to be efficiently implemented on Spartan-3 field programmable gate array (FPGA) board. The implementation results showed time, area savings up to 44.7%, 14.3%, respectively, which indicates that these adders are very effective for designs with critical timing requirements.

Keywords

Residue Number System, modulo 2n+/-1 adders, FPGA, prefix carry computation

RIV year

2011

Released

19.05.2011

ISBN

978-80-214-4404-1

Book

IMAPS - Mikroelektronika současnosti

Pages from

1

Pages to

6

Pages count

6

BibTex


@inproceedings{BUT88544,
  author="Dina {Younes} and Pavel {Šteffan}",
  title="TWO MODULO 2n +/- 1 ADDERS BASED ON PREFIX COMPUTATION",
  annote="Two novel designs of residue number system adders corresponding moduli    2n–1, 2n+1 are presented in this paper. Both designs are based on prefix computation idea, which was inspired from the technique used in carry look-ahead adder (CLA). This prefix computation speeds up the addition-correction process corresponding to each modulo. The proposed modular adders were designed in such a way to be efficiently implemented on Spartan-3 field programmable gate array (FPGA) board. The implementation results showed time, area savings up to 44.7%, 14.3%, respectively, which indicates that these adders are very effective for designs with critical timing requirements.",
  booktitle="IMAPS - Mikroelektronika současnosti",
  chapter="88544",
  howpublished="print",
  year="2011",
  month="may",
  pages="1--6",
  type="conference paper"
}