Publication detail

Hardware Accelerated Functional Verification - Framework for FPGA-Accelerated Functional Verification

ZACHARIÁŠOVÁ, M.

Original Title

Hardware Accelerated Functional Verification - Framework for FPGA-Accelerated Functional Verification

English Title

Hardware Accelerated Functional Verification - Framework for FPGA-Accelerated Functional Verification

Type

book

Language

en

Original Abstract

Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. This thesis introduces a design of a verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification, while retaining the possibility to run verification also in the user-friendly debugging environment of a simulator. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM) as well as assertion-based verification, making its application range quite large. According to the experiments carried out on a prototype implementation, the achieved acceleration is proportional to the number of checked transactions and the complexity of the verified system. The maximum acceleration achieved on the set of experiments was over 130 times.

English abstract

Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. This thesis introduces a design of a verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification, while retaining the possibility to run verification also in the user-friendly debugging environment of a simulator. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM) as well as assertion-based verification, making its application range quite large. According to the experiments carried out on a prototype implementation, the achieved acceleration is proportional to the number of checked transactions and the complexity of the verified system. The maximum acceleration achieved on the set of experiments was over 130 times.

Keywords

functional verification, FPGA, acceleration, SystemVerilog

RIV year

2011

Released

02.12.2011

Publisher

Lambert Academic Publishing

Location

Saarbrucken

ISBN

978-3-8465-5913-0

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages count

60

Documents

BibTex


@book{BUT76509,
  author="Marcela {Zachariášová}",
  title="Hardware Accelerated Functional Verification - Framework for FPGA-Accelerated Functional Verification",
  annote="Functional verification is a widespread technique to check whether a hardware
system satisfies a given correctness specification. As the complexity of modern
hardware systems rises rapidly, it is a challenging task to find appropriate
techniques for acceleration of this process. This thesis introduces a design of
a verification framework that exploits the field-programmable gate array (FPGA)
technology for cycle-accurate acceleration of simulation-based verification,
while retaining the possibility to run verification also in the user-friendly
debugging environment of a simulator. The presented framework is written in
SystemVerilog and complies with the principles of functional verification
methodologies (OVM, UVM) as well as assertion-based verification, making its
application range quite large. According to the experiments carried out on
a prototype implementation, the achieved acceleration is proportional to the
number of checked transactions and the complexity of the verified system. The
maximum acceleration achieved on the set of experiments was over 130 times.",
  address="Lambert Academic Publishing",
  chapter="76509",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Lambert Academic Publishing",
  year="2011",
  month="december",
  pages="0--0",
  publisher="Lambert Academic Publishing",
  type="book"
}