Publication detail

Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity

KOŠAŘ, V. KOŘENEK, J.

Original Title

Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions in FPGA. Proposed reduction is able to decrease the number of states by more than 32% and the amount of transitions by more than 31%. The amount of look-up tables is reduced by more than 15% and the amount of flip-flops by more than 34%.

Keywords

FPGA, NFA, reduction, regular expression matching

Authors

KOŠAŘ, V.; KOŘENEK, J.

RIV year

2011

Released

13. 4. 2011

Publisher

IEEE Computer Society

Location

Cottbus

ISBN

978-1-4244-9753-9

Book

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

Pages from

401

Pages to

402

Pages count

2

URL

https://www.fit.vut.cz/research/publication/9766/

BibTex

@inproceedings{BUT76456,
  author="Vlastimil {Košař} and Jan {Kořenek}",
  title="Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  year="2011",
  pages="401--402",
  publisher="IEEE Computer Society",
  address="Cottbus",
  isbn="978-1-4244-9753-9",
  url="https://www.fit.vut.cz/research/publication/9766/"
}