Publication detail

SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

STRAKA, M. KAŠTIL, J. KOTÁSEK, Z.

Original Title

SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

English Title

SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

Type

conference paper

Language

en

Original Abstract

In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.

English abstract

In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.

Keywords

SEU, simulatotion, generator, framework, online testing, fault tolerance

RIV year

2011

Released

26.04.2011

Publisher

IEEE Computer Society

Location

Oulu

ISBN

978-0-7695-4494-6

Book

14th EUROMICRO Conference on Digital System Design

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

223

Pages to

230

Pages count

8

URL

Documents

BibTex


@inproceedings{BUT76320,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems",
  annote="In the paper, the SEU simulation framework for testing fault tolerant system
designs implemented into FPGA is presented. The framework is based on SEU
generation outside FPGA (in personal computer) and the transport of modified
bitstream through the JTAG interface and subsequent  dynamic reconfiguration of 
FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator
does not require any changes in the tested design and is fully independent on the
function implemented into FPGA. The requirements on the SEU generator and its
properties are described in the paper as well. The external SEU generator for
Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5
for different types of RTL circuits and fault tolerant architectures. The
experimatal results demonstrated the effectiveness of the methodology.",
  address="IEEE Computer Society",
  booktitle="14th EUROMICRO Conference on Digital System Design",
  chapter="76320",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2011",
  month="april",
  pages="223--230",
  publisher="IEEE Computer Society",
  type="conference paper"
}