Publication detail

Decreasing Test Time by Scan Chain Reorganization

BARTOŠ, P. KOTÁSEK, Z. DOHNAL, J.

Original Title

Decreasing Test Time by Scan Chain Reorganization

English Title

Decreasing Test Time by Scan Chain Reorganization

Type

conference paper

Language

en

Original Abstract

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

English abstract

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

Keywords

scan chain, test, time, reordering, reorganization, physical, layout

RIV year

2011

Released

13.04.2011

Publisher

IEEE Computer Society

Location

Cottbus

ISBN

978-1-4244-9753-9

Book

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

371

Pages to

374

Pages count

4

BibTex


@inproceedings{BUT76306,
  author="Pavel {Bartoš} and Zdeněk {Kotásek} and Jan {Dohnal}",
  title="Decreasing Test Time by Scan Chain Reorganization",
  annote="In this paper, methodology for scan chain optimisation performed after physical
layout is presented. It is shown how the methodology can be used to decrease test
time of component under test if scan chain is reorganized. The principles of the
methodology are based on eliminating some types of faults in the physical layout
and subsequent reduction of the number of test vectors needed to test the scan
chain. As a result, component test application time is decreased. The methodology
was verified on several circuits, experimental results are provided and
discussed. It is expected that the results of our methodology can be used in mass
production of electronic components where any reduction of test time is of great
importance.",
  address="IEEE Computer Society",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  chapter="76306",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2011",
  month="april",
  pages="371--374",
  publisher="IEEE Computer Society",
  type="conference paper"
}