Publication detail

Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA

STRAKA, M. KAŠTIL, J. NOVOTNÝ, J. KOTÁSEK, Z.

Original Title

Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA

English Title

Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA

Type

conference paper

Language

en

Original Abstract

In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform.

English abstract

In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform.

Keywords

FPGA, fault tolerant, bus, multicore, reconfiguration, on-line checker, TMR

RIV year

2011

Released

25.02.2011

Publisher

IEEE Computer Society

Location

Cottbus

ISBN

978-1-4244-9753-9

Book

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

397

Pages to

398

Pages count

2

BibTex


@inproceedings{BUT76277,
  author="Martin {Straka} and Jan {Kaštil} and Jaroslav {Novotný} and Zdeněk {Kotásek}",
  title="Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA",
  annote="In the paper, a technique for design of highly dependable communication structure
in SRAM-based FPGA is presented. The architecture of the multicore system and the
structure of fault tolerant bus with cache memories are demonstrated. The fault
tolerant properties are achieved by the replication and utilization of the self
checking techniques together with partial dynamic reconfiguration. The
experimental results show that presented system has small overhead if the high
number of function units are used in the dependable system. All experiments were
done on the Virtex5 and Virtex6 platform.",
  address="IEEE Computer Society",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  chapter="76277",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2011",
  month="february",
  pages="397--398",
  publisher="IEEE Computer Society",
  type="conference paper"
}