Publication detail

Imaging Algorithm Speedup Using Co-Design

ZEMČÍK, P., FUČÍK, O., RICHTER, M., VALENTA, P.

Original Title

Imaging Algorithm Speedup Using Co-Design

English Title

Imaging Algorithm Speedup Using Co-Design

Type

conference paper

Language

en

Original Abstract

The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA.

English abstract

The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA.

Keywords

co-design, image processing, FPGA

Released

11.06.2001

Publisher

Faculty of Electrical Engineering and Informatics, University of Technology Košice

Location

Štrbské Pleso

ISBN

80-227-1542-5

Book

Summaries Volume Process Control 01

Pages from

96

Pages to

97

Pages count

2

Documents

BibTex


@inproceedings{BUT5744,
  author="Pavel {Zemčík} and Otto {Fučík} and Miloslav {Richter} and Pavel {Valenta}",
  title="Imaging Algorithm Speedup Using Co-Design",
  annote="The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA.",
  address="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  booktitle="Summaries Volume Process Control 01",
  chapter="5744",
  institution="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  year="2001",
  month="june",
  pages="96--97",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  type="conference paper"
}