Publication detail

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

DVOŘÁK, V.

Original Title

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

English Title

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

Type

conference paper

Language

en

Original Abstract

The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

English abstract

The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

Keywords

Parallel Embedded Systems, Multiprocessor Simulation, Hardware Description Language

RIV year

2001

Released

01.01.2001

Publisher

Publishing House of Zielona Gora Technical University

Location

Przytok near Zielona Gora, POLAND

ISBN

83-85911-62-6

Book

Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01

Pages from

103

Pages to

108

Pages count

6

Documents

BibTex


@inproceedings{BUT5579,
  author="Václav {Dvořák}",
  title="Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study",
  annote="The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either  bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line,  as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.",
  address="Publishing House of Zielona Gora Technical University",
  booktitle="Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01",
  chapter="5579",
  institution="Publishing House of Zielona Gora Technical University",
  year="2001",
  month="january",
  pages="103--108",
  publisher="Publishing House of Zielona Gora Technical University",
  type="conference paper"
}