Publication detail

Basic Block of Pipelined ADC Design Requirements

KLEDROWETZ, V. HÁZE, J.

Original Title

Basic Block of Pipelined ADC Design Requirements

English Title

Basic Block of Pipelined ADC Design Requirements

Type

journal article

Language

en

Original Abstract

The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to-Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.

English abstract

The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to-Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.

Keywords

Pipelined ADC, MDAC, SC technique, MATLAB model, thermal noise, opamp.

RIV year

2011

Released

11.04.2011

Publisher

VUT v Brně

Location

Brno

Pages from

234

Pages to

238

Pages count

5

BibTex


@article{BUT50694,
  author="Vilém {Kledrowetz} and Jiří {Háze}",
  title="Basic Block of Pipelined ADC Design Requirements",
  annote="The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to-Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.",
  address="VUT v Brně",
  chapter="50694",
  institution="VUT v Brně",
  number="1",
  volume="2011",
  year="2011",
  month="april",
  pages="234--238",
  publisher="VUT v Brně",
  type="journal article"
}