Publication detail

Evolutionary Functional Recovery in Virtual Reconfigurable Circuits

SEKANINA, L.

Original Title

Evolutionary Functional Recovery in Virtual Reconfigurable Circuits

English Title

Evolutionary Functional Recovery in Virtual Reconfigurable Circuits

Type

journal article - other

Language

en

Original Abstract

A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices. 

English abstract

A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices. 

Keywords

hardware, logic design, reliability, reconfigurable circuit, evolutionary algorithm

RIV year

2007

Released

30.07.2007

Pages from

1

Pages to

22

Pages count

22

BibTex


@article{BUT45162,
  author="Lukáš {Sekanina}",
  title="Evolutionary Functional Recovery in Virtual Reconfigurable Circuits",
  annote="A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device
developed using an ordinary FPGA in order to easily implement evolvable hardware
applications. While a fast partial run-time reconfiguration and
application-specific programmable elements represent the main advantages of VRC,
the main disadvantage of the VRC is the area consumed. This study describes
experiments conducted to estimate how the use of VRC influences the dependability
of FPGA-based evolvable systems. It is shown that these systems are not as
sensitive to faults as their area-demanding implementations might suggest. An
evolutionary algorithm is utilized to design fault tolerant circuits as well as
to perform an automatic functional recovery when faults are detected in the
configuration memory of the FPGA. All the experiments are performed on models of
reconfigurable devices. ",
  chapter="45162",
  howpublished="print",
  journal="ACM Journal on Emerging Technologies in Computing Systems",
  number="2",
  volume="3",
  year="2007",
  month="july",
  pages="1--22",
  type="journal article - other"
}