Publication detail

Pipelined ADC Design Requirements

KLEDROWETZ, V.

Original Title

Pipelined ADC Design Requirements

Type

conference paper

Language

English

Original Abstract

The presented work deals with design and analysis of a pipelined analog-to-digital converter (ADC). There exist error sources such as finite DC gain of opamp, capacitor mismatch, opamp bandwidth, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These error sources are explained and their influences on overall parameters of the pipelined ADC are studied. The pipelined ADC was simulated in MATLAB-Simulink and CADENCE simulation environment.

Keywords

Pipelined ADC, MDAC, opamp

Authors

KLEDROWETZ, V.

RIV year

2011

Released

28. 4. 2011

Publisher

NOVPRESS s.r.o.

Location

Brno

ISBN

978-80-214-4273-3

Book

Proceedings of the 17th Conference STUDENT EEICT 2011

Edition

vol. 3

Edition number

1

Pages from

407

Pages to

411

Pages count

5

BibTex

@inproceedings{BUT36713,
  author="Vilém {Kledrowetz}",
  title="Pipelined ADC Design Requirements",
  booktitle="Proceedings of the 17th Conference STUDENT EEICT 2011",
  year="2011",
  series="vol. 3",
  number="1",
  pages="407--411",
  publisher="NOVPRESS s.r.o.",
  address="Brno",
  isbn="978-80-214-4273-3"
}