Publication detail

Design and Debugging of Parallel Architectures Using the ISAC Language

PŘIKRYL, Z. KŘOUSTEK, J. HRUŠKA, T. KOLÁŘ, D. MASAŘÍK, K. HUSÁR, A.

Original Title

Design and Debugging of Parallel Architectures Using the ISAC Language

English Title

Design and Debugging of Parallel Architectures Using the ISAC Language

Type

conference paper

Language

en

Original Abstract

Trend of nowadays embedded systems is placing more than one application-specific instruction set processor (ASIP) on one chip (multi-processor systems on a chip). This allows parallel processing of multimedia and network applications, where input is usually a data stream. Each of these processors is highly optimized for a specific task. Other forms of suitable parallel architectures are very long instruction word processors (VLIW) and multi-core processors. These parallel architectures are often used in multi-processor systems on a chip. Architecture description languages (ADL) are very effective for description of simple processors. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in these languages. Therefore, we introduce new constructions of an architecture description language ISAC allowing easy and fast prototyping of such processors and systems.

English abstract

Trend of nowadays embedded systems is placing more than one application-specific instruction set processor (ASIP) on one chip (multi-processor systems on a chip). This allows parallel processing of multimedia and network applications, where input is usually a data stream. Each of these processors is highly optimized for a specific task. Other forms of suitable parallel architectures are very long instruction word processors (VLIW) and multi-core processors. These parallel architectures are often used in multi-processor systems on a chip. Architecture description languages (ADL) are very effective for description of simple processors. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in these languages. Therefore, we introduce new constructions of an architecture description language ISAC allowing easy and fast prototyping of such processors and systems.

Keywords

Architecture description language, ISAC, VLIW, multiprocessor system on a chip, simulation, debugging

RIV year

2010

Released

01.11.2010

Publisher

Global Science & Technology Forum

Location

Singapore

ISBN

978-981-08-7656-2

Book

Proceedings ot the Annual International Conference on Advanced Distributed and Parallel Computing and Real-Time and Embedded Systems

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

213

Pages to

221

Pages count

9

BibTex


@inproceedings{BUT35126,
  author="Zdeněk {Přikryl} and Jakub {Křoustek} and Tomáš {Hruška} and Dušan {Kolář} and Karel {Masařík} and Adam {Husár}",
  title="Design and Debugging of Parallel Architectures Using the ISAC Language",
  annote="Trend of nowadays embedded systems is placing more than one application-specific
instruction set processor (ASIP) on one chip (multi-processor systems on a chip).
This allows parallel processing of multimedia and network applications, where
input is usually a data stream. Each of these processors is highly optimized for
a specific task. Other forms of suitable parallel architectures are very long
instruction word processors (VLIW) and multi-core processors. These parallel
architectures are often used in multi-processor systems on a chip.

Architecture description languages (ADL) are very effective for 
description of simple processors. However, support for description of parallel
architectures and multi-processor systems is very low or completely missing in
these languages. Therefore, 
we introduce new constructions of an architecture description language ISAC
allowing easy and fast prototyping of such processors and systems.",
  address="Global Science & Technology Forum",
  booktitle="Proceedings ot the Annual International Conference on Advanced Distributed and Parallel Computing and Real-Time and Embedded Systems",
  chapter="35126",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Global Science & Technology Forum",
  year="2010",
  month="november",
  pages="213--221",
  publisher="Global Science & Technology Forum",
  type="conference paper"
}