Publication detail

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

STRAKA, M. KAŠTIL, J. KOTÁSEK, Z.

Original Title

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Keywords

fault tolerant systems, reconfiguration, controller, FPGA, architecture

Authors

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.

RIV year

2010

Released

26. 4. 2010

Publisher

IEEE Computer Society

Location

Lille

ISBN

978-0-7695-4171-6

Book

13th EUROMICRO Conference on Digital System Design, DSD'2010

Pages from

365

Pages to

372

Pages count

8

BibTex

@inproceedings{BUT34654,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration",
  booktitle="13th EUROMICRO Conference on Digital System Design, DSD'2010",
  year="2010",
  pages="365--372",
  publisher="IEEE Computer Society",
  address="Lille",
  isbn="978-0-7695-4171-6"
}