Publication detail

Fast Packet Classification Algorithm in Hardware

PUŠ, V.

Original Title

Fast Packet Classification Algorithm in Hardware

English Title

Fast Packet Classification Algorithm in Hardware

Type

conference paper

Language

en

Original Abstract

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. I propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved.

English abstract

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. I propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved.

Keywords

Packet classification, hardware

RIV year

2008

Released

01.12.2008

Publisher

NEUVEDEN

Location

Vídeň

ISBN

978-3-200-01612-5

Book

Junior Scientist Conference 2008

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

65

Pages to

66

Pages count

2

BibTex


@inproceedings{BUT33439,
  author="Viktor {Puš}",
  title="Fast Packet Classification Algorithm in Hardware",
  annote="Packet classification is an important operation for applications such as
routers, firewalls or intrusion detection systems. Many algorithms and
hardware architectures for packet classification have been created, but
none of them can compete with the speed of TCAMs in the worst case. 
I propose new
hardware-based algorithm for packet classification. The solution is based
on problem decomposition and is aimed at the highest network speeds. A unique
property of the algorithm is the constant time complexity in terms of
external memory accesses. The algorithm performs exactly two external
memory accesses to classify a packet. Using FPGA and one commodity SRAM
chip, a throughput of 150 million packets per second can be achieved.",
  address="NEUVEDEN",
  booktitle="Junior Scientist Conference 2008",
  chapter="33439",
  edition="NEUVEDEN",
  howpublished="print",
  institution="NEUVEDEN",
  year="2008",
  month="december",
  pages="65--66",
  publisher="NEUVEDEN",
  type="conference paper"
}