Publication detail

On Lookup Table Cascade-Based Realizations of Arbiters

MIKUŠEK, P. DVOŘÁK, V.

Original Title

On Lookup Table Cascade-Based Realizations of Arbiters

English Title

On Lookup Table Cascade-Based Realizations of Arbiters

Type

conference paper

Language

en

Original Abstract

This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.

English abstract

This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.

Keywords

LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits

RIV year

2008

Released

08.06.2008

Publisher

IEEE Computer Society

Location

Parma

ISBN

978-0-7695-3277-6

Book

11th EUROMICRO Conference on Digital System Design DSD 2008

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

795

Pages to

802

Pages count

8

URL

Documents

BibTex


@inproceedings{BUT32056,
  author="Petr {Mikušek} and Václav {Dvořák}",
  title="On Lookup Table Cascade-Based Realizations of Arbiters",
  annote="This paper presents a new algorithm of iterative decomposition for
multiple-output Boolean functions with an embedded heuristics to order variables.
The algorithm produces a cascade of look-up tables (LUTs) that implements the
given function and simultaneously a sub-optimal Multi-Terminal Binary Decision
Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs
with BRAMs or at a non-traditional synthesis of large combinational and
sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes
for efficient firmware implementation, especially when a micro-programmed
controller that firmware runs on supports multi-way branching. A novel technique
is illustrated on practical examples of three types of arbiters. It may be quite
useful as a more flexible alternative implementation of digital systems with
increased testability and improved manufacturability.",
  address="IEEE Computer Society",
  booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008",
  chapter="32056",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2008",
  month="june",
  pages="795--802",
  publisher="IEEE Computer Society",
  type="conference paper"
}