Publication detail

DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM

ŠTEFFAN, P. ZOŠIAK, D.

Original Title

DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM

English Title

DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM

Type

conference paper

Language

en

Original Abstract

This application note contains detail description and implementation of digital phase-locked loop (for short DPLL) designed by using VHSIC hardware description language (for short VHDL). This programming language was developed for hardware design of microchips and digital circuits, later adapted for programming FPGA and CPLD circuits. FPGAs and CPLDs are very useful for making design models, so we are able to test the design before fabrication. DPLL is analogous to PLL constructed from analog electronic components. Wide usage (FM demodulation, FSK demodulation, tone decoding, frequency multiplication, clock synchronization) makes from DPLL or PLL important electronic component in signal processing and digital systems. Design described in this paper was used as clock recovery and input data synchronization system by implementation of USB protocol into FPGA circuit again by using VHD language.

English abstract

This application note contains detail description and implementation of digital phase-locked loop (for short DPLL) designed by using VHSIC hardware description language (for short VHDL). This programming language was developed for hardware design of microchips and digital circuits, later adapted for programming FPGA and CPLD circuits. FPGAs and CPLDs are very useful for making design models, so we are able to test the design before fabrication. DPLL is analogous to PLL constructed from analog electronic components. Wide usage (FM demodulation, FSK demodulation, tone decoding, frequency multiplication, clock synchronization) makes from DPLL or PLL important electronic component in signal processing and digital systems. Design described in this paper was used as clock recovery and input data synchronization system by implementation of USB protocol into FPGA circuit again by using VHD language.

Keywords

synchronization, recovery, VHDL, CPLL, FPGA

Released

10.09.2009

Publisher

Ing. Zdeněk Novotný

Location

Brno

ISBN

978-80-214-3717-3

Book

Electronic Devices and Systems EDS 08

Edition

první

Edition number

1

Pages from

383

Pages to

389

Pages count

7

BibTex


@inproceedings{BUT30787,
  author="Pavel {Šteffan} and Dušan {Zošiak}",
  title="DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM",
  annote="This application note contains detail description and implementation of digital phase-locked loop (for short DPLL) designed by using VHSIC hardware description language (for short VHDL). This programming language was developed for hardware design of microchips and digital circuits, later adapted for programming FPGA and CPLD circuits. FPGAs and CPLDs are very useful for making design models, so we are able to test the design before fabrication. DPLL is analogous to PLL constructed from analog electronic components.  Wide usage (FM demodulation, FSK demodulation, tone decoding, frequency multiplication, clock synchronization) makes from DPLL or PLL important electronic component in signal processing and digital systems. Design described in this paper was used as clock recovery and input data synchronization system by implementation of USB protocol into FPGA circuit again by using VHD language.",
  address="Ing. Zdeněk Novotný",
  booktitle="Electronic Devices and Systems EDS 08",
  chapter="30787",
  edition="první",
  howpublished="print",
  institution="Ing. Zdeněk Novotný",
  year="2009",
  month="september",
  pages="383--389",
  publisher="Ing. Zdeněk Novotný",
  type="conference paper"
}