Publication detail

Online Protocol Testing for FPGA Based Fault Tolerant Systems

TOBOLA, J. KOTÁSEK, Z. KOŘENEK, J. MARTÍNEK, T. STRAKA, M.

Original Title

Online Protocol Testing for FPGA Based Fault Tolerant Systems

English Title

Online Protocol Testing for FPGA Based Fault Tolerant Systems

Type

conference paper

Language

en

Original Abstract

In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be performed - in the paper the lowest level is presented. The definition of dedicated language for the description of possible communication faults is presented. The core generator is used to produce VHDL code describing the behaviour of the checker.

English abstract

In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be performed - in the paper the lowest level is presented. The definition of dedicated language for the description of possible communication faults is presented. The core generator is used to produce VHDL code describing the behaviour of the checker.

Keywords

Communication Protocol Testing, Fault Tolerant Systems, Checker, FPGA, VHDL

RIV year

2007

Released

29.08.2007

Publisher

IEEE Computer Society

Location

Lubeck, Germany

ISBN

0-7695-2978-X

Book

10th EUROMICRO Conference on Digital System Design DSD 2007

Pages from

676

Pages to

679

Pages count

4

Documents

BibTex


@inproceedings{BUT28607,
  author="Jiří {Tobola} and Zdeněk {Kotásek} and Jan {Kořenek} and Tomáš {Martínek} and Martin {Straka}",
  title="Online Protocol Testing for FPGA Based Fault Tolerant Systems",
  annote="In this paper, the methodology for automated design of checker for
communication protocol testing is presented. Based on the level of
checking, different design strategies can be performed - in the
paper the lowest level is presented. The definition of dedicated
language for the description of possible communication faults is
presented. The core generator is used to produce VHDL code
describing the behaviour of the checker.",
  address="IEEE Computer Society",
  booktitle="10th EUROMICRO Conference on Digital System Design DSD 2007",
  chapter="28607",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2007",
  month="august",
  pages="676--679",
  publisher="IEEE Computer Society",
  type="conference paper"
}