Publication detail

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA, L.

Original Title

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

English Title

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

Type

conference paper

Language

en

Original Abstract

TBD

English abstract

TBD

Keywords

digital circuit, polymorphic gate, adder, testing

RIV year

2007

Released

19.04.2007

Publisher

IEEE Computer Society

Location

Gliwice

ISBN

1424411610

Book

2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

Pages from

243

Pages to

246

Pages count

4

Documents

BibTex


@inproceedings{BUT28586,
  author="Lukáš {Sekanina}",
  title="Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
  annote="TBD",
  address="IEEE Computer Society",
  booktitle="2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  chapter="28586",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2007",
  month="april",
  pages="243--246",
  publisher="IEEE Computer Society",
  type="conference paper"
}