Publication detail

TCAD simulation of drain-induced barrier lowering

RECMAN Milan

Original Title

TCAD simulation of drain-induced barrier lowering

English Title

TCAD simulation of drain-induced barrier lowering

Type

conference paper

Language

en

Original Abstract

For short channel MOSFETs, the threshold voltage is reduced if the drain bias is increased and this short-channel effect (SCE) is known as drain-induced barrier lowering (DIBL). The contribution deals with TCAD simulation of DIBL. The method to extract the threshold voltage reduction and the subthreshold current increase due to DIBL is described. The experiment contains five different NMOSFET device simulations in order to illustrate drain-induced barrier lowering. The simulations are run under GENESISe. The tool flow starts with the device editor MDRAW followed by device simulator DESSIS and visualization and extraction tool INSPECT.

English abstract

For short channel MOSFETs, the threshold voltage is reduced if the drain bias is increased and this short-channel effect (SCE) is known as drain-induced barrier lowering (DIBL). The contribution deals with TCAD simulation of DIBL. The method to extract the threshold voltage reduction and the subthreshold current increase due to DIBL is described. The experiment contains five different NMOSFET device simulations in order to illustrate drain-induced barrier lowering. The simulations are run under GENESISe. The tool flow starts with the device editor MDRAW followed by device simulator DESSIS and visualization and extraction tool INSPECT.

Keywords

Device simulation, Electrical simulation, Parameter extraction, Device modeling, Curve fitting, Device optimization. 2D, Threshold voltage, Drain-induced barrier lowering.

Released

01.01.2006

Publisher

Nakl. Novotný

Location

Brno

ISBN

960-8025-99-8

Book

Electronic System Design 2006, Socrates International Conference Proceedings Chania, October 16 – 17, 2006, Greece

Pages from

76

Pages to

79

Pages count

4

BibTex


@inproceedings{BUT24694,
  author="Milan {Recman}",
  title="TCAD simulation of drain-induced barrier lowering",
  annote="For short channel MOSFETs, the threshold voltage is reduced if the drain bias is increased and this short-channel effect (SCE) is known as drain-induced barrier lowering (DIBL). The contribution deals with TCAD simulation of DIBL. The method to extract  the threshold voltage reduction and the subthreshold current increase due to DIBL is described. The experiment contains five different NMOSFET device simulations in order to illustrate drain-induced barrier lowering. The simulations are run under GENESISe. The tool flow starts with the device editor MDRAW followed by device simulator DESSIS and visualization and extraction tool INSPECT.",
  address="Nakl. Novotný",
  booktitle="Electronic System Design 2006, Socrates International Conference Proceedings Chania, October 16 – 17, 2006, Greece",
  chapter="24694",
  institution="Nakl. Novotný",
  year="2006",
  month="january",
  pages="76",
  publisher="Nakl. Novotný",
  type="conference paper"
}