Publication detail

FPGA Implementation of an SDDR Core for Radio Transceiver

BOBULA, M.

Original Title

FPGA Implementation of an SDDR Core for Radio Transceiver

Type

conference paper

Language

English

Original Abstract

Today technology and efficiency of the hardware components intended for the digital signal processing offers a great potential to revolutionize the way how radio transceivers are designed. The potential to create the IF sampled software defined digital radio (SDDR) cores for the traditional analog systems, as well as for the modern digital communication transceivers utilizing digital techniques of modulation, algorithms of the adaptation, synchronization, and decoding, completely in the digital domain. This work offers a prototype of such SDDR core for the radio data modem implemented mainly in an FPGA. The design itself was preceded by a complete simulation in MATLAB, Simulink.

Keywords

M-CPFSK, SDR, narrowband radio, dynamic range, FPGA, ADC

Authors

BOBULA, M.

RIV year

2006

Released

27. 4. 2006

Publisher

Ing. Zdeněk Novotný CSc., Ondráčkova 105, Brno

Location

VUT BRNO

ISBN

80-214-3161-X

Book

Proceedings of the 12th Conference STUDENT EEICT 2006, Volume 2

Pages from

14

Pages to

16

Pages count

3

BibTex

@inproceedings{BUT23837,
  author="Marek {Bobula}",
  title="FPGA Implementation of an SDDR Core for Radio Transceiver",
  booktitle="Proceedings of the 12th Conference STUDENT EEICT 2006, Volume 2",
  year="2006",
  pages="3",
  publisher="Ing. Zdeněk Novotný CSc., Ondráčkova 105, Brno",
  address="VUT BRNO",
  isbn="80-214-3161-X"
}